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Soby Mathewd29f67b2016-05-05 12:31:57 +01001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#ifndef __ASM_MACROS_S__
31#define __ASM_MACROS_S__
32
33#include <arch.h>
34#include <asm_macros_common.S>
35
36#define WORD_SIZE 4
37
38 /*
39 * Co processor register accessors
40 */
41 .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2
42 mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2
43 .endm
44
45 .macro ldcopr16 reg1, reg2, coproc, opc1, CRm
46 mrrc \coproc, \opc1, \reg1, \reg2, \CRm
47 .endm
48
49 .macro stcopr reg, coproc, opc1, CRn, CRm, opc2
50 mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2
51 .endm
52
53 .macro stcopr16 reg1, reg2, coproc, opc1, CRm
54 mcrr \coproc, \opc1, \reg1, \reg2, \CRm
55 .endm
56
57 /* Cache line size helpers */
58 .macro dcache_line_size reg, tmp
59 ldcopr \tmp, CTR
60 ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH
61 mov \reg, #WORD_SIZE
62 lsl \reg, \reg, \tmp
63 .endm
64
65 .macro icache_line_size reg, tmp
66 ldcopr \tmp, CTR
67 and \tmp, \tmp, #CTR_IMINLINE_MASK
68 mov \reg, #WORD_SIZE
69 lsl \reg, \reg, \tmp
70 .endm
71
72 /*
Yatharth Kocharf528faf2016-06-28 16:58:26 +010073 * Declare the exception vector table, enforcing it is aligned on a
74 * 32 byte boundary.
75 */
76 .macro vector_base label
77 .section .vectors, "ax"
78 .align 5
79 \label:
80 .endm
81
82 /*
Soby Mathewd29f67b2016-05-05 12:31:57 +010083 * This macro calculates the base address of the current CPU's multi
84 * processor(MP) stack using the plat_my_core_pos() index, the name of
85 * the stack storage and the size of each stack.
86 * Out: r0 = physical address of stack base
87 * Clobber: r14, r1, r2
88 */
89 .macro get_my_mp_stack _name, _size
90 bl plat_my_core_pos
91 ldr r2, =(\_name + \_size)
92 mov r1, #\_size
93 mla r0, r0, r1, r2
94 .endm
95
96 /*
97 * This macro calculates the base address of a uniprocessor(UP) stack
98 * using the name of the stack storage and the size of the stack
99 * Out: r0 = physical address of stack base
100 */
101 .macro get_up_stack _name, _size
102 ldr r0, =(\_name + \_size)
103 .endm
104
105#endif /* __ASM_MACROS_S__ */