blob: 79a54045a727dc75035de1971b82f2d1671f8942 [file] [log] [blame]
Haojian Zhuang5f281b32017-05-24 08:45:05 +08001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __HI6220_AO_H__
8#define __HI6220_AO_H__
9
10#define AO_CTRL_BASE 0xF7800000
11
12#define AO_SC_SYS_CTRL0 (AO_CTRL_BASE + 0x000)
13#define AO_SC_SYS_CTRL1 (AO_CTRL_BASE + 0x004)
14#define AO_SC_SYS_CTRL2 (AO_CTRL_BASE + 0x008)
15#define AO_SC_SYS_STAT0 (AO_CTRL_BASE + 0x010)
16#define AO_SC_SYS_STAT1 (AO_CTRL_BASE + 0x014)
17#define AO_SC_MCU_IMCTRL (AO_CTRL_BASE + 0x018)
18#define AO_SC_MCU_IMSTAT (AO_CTRL_BASE + 0x01C)
19#define AO_SC_SECONDRY_INT_EN0 (AO_CTRL_BASE + 0x044)
20#define AO_SC_SECONDRY_INT_STATR0 (AO_CTRL_BASE + 0x048)
21#define AO_SC_SECONDRY_INT_STATM0 (AO_CTRL_BASE + 0x04C)
22#define AO_SC_MCU_WKUP_INT_EN6 (AO_CTRL_BASE + 0x054)
23#define AO_SC_MCU_WKUP_INT_STATR6 (AO_CTRL_BASE + 0x058)
24#define AO_SC_MCU_WKUP_INT_STATM6 (AO_CTRL_BASE + 0x05C)
25#define AO_SC_MCU_WKUP_INT_EN5 (AO_CTRL_BASE + 0x064)
26#define AO_SC_MCU_WKUP_INT_STATR5 (AO_CTRL_BASE + 0x068)
27#define AO_SC_MCU_WKUP_INT_STATM5 (AO_CTRL_BASE + 0x06C)
28#define AO_SC_MCU_WKUP_INT_EN4 (AO_CTRL_BASE + 0x094)
29#define AO_SC_MCU_WKUP_INT_STATR4 (AO_CTRL_BASE + 0x098)
30#define AO_SC_MCU_WKUP_INT_STATM4 (AO_CTRL_BASE + 0x09C)
31#define AO_SC_MCU_WKUP_INT_EN0 (AO_CTRL_BASE + 0x0A8)
32#define AO_SC_MCU_WKUP_INT_STATR0 (AO_CTRL_BASE + 0x0AC)
33#define AO_SC_MCU_WKUP_INT_STATM0 (AO_CTRL_BASE + 0x0B0)
34#define AO_SC_MCU_WKUP_INT_EN1 (AO_CTRL_BASE + 0x0B4)
35#define AO_SC_MCU_WKUP_INT_STATR1 (AO_CTRL_BASE + 0x0B8)
36#define AO_SC_MCU_WKUP_INT_STATM1 (AO_CTRL_BASE + 0x0BC)
37#define AO_SC_INT_STATR (AO_CTRL_BASE + 0x0C4)
38#define AO_SC_INT_STATM (AO_CTRL_BASE + 0x0C8)
39#define AO_SC_INT_CLEAR (AO_CTRL_BASE + 0x0CC)
40#define AO_SC_INT_EN_SET (AO_CTRL_BASE + 0x0D0)
41#define AO_SC_INT_EN_DIS (AO_CTRL_BASE + 0x0D4)
42#define AO_SC_INT_EN_STAT (AO_CTRL_BASE + 0x0D8)
43#define AO_SC_INT_STATR1 (AO_CTRL_BASE + 0x0E4)
44#define AO_SC_INT_STATM1 (AO_CTRL_BASE + 0x0E8)
45#define AO_SC_INT_CLEAR1 (AO_CTRL_BASE + 0x0EC)
46#define AO_SC_INT_EN_SET1 (AO_CTRL_BASE + 0x0F0)
47#define AO_SC_INT_EN_DIS1 (AO_CTRL_BASE + 0x0F4)
48#define AO_SC_INT_EN_STAT1 (AO_CTRL_BASE + 0x0F8)
49#define AO_SC_TIMER_EN0 (AO_CTRL_BASE + 0x1D0)
50#define AO_SC_TIMER_EN1 (AO_CTRL_BASE + 0x1D4)
51#define AO_SC_TIMER_EN4 (AO_CTRL_BASE + 0x1F0)
52#define AO_SC_TIMER_EN5 (AO_CTRL_BASE + 0x1F4)
53#define AO_SC_MCU_SUBSYS_CTRL0 (AO_CTRL_BASE + 0x400)
54#define AO_SC_MCU_SUBSYS_CTRL1 (AO_CTRL_BASE + 0x404)
55#define AO_SC_MCU_SUBSYS_CTRL2 (AO_CTRL_BASE + 0x408)
56#define AO_SC_MCU_SUBSYS_CTRL3 (AO_CTRL_BASE + 0x40C)
57#define AO_SC_MCU_SUBSYS_CTRL4 (AO_CTRL_BASE + 0x410)
58#define AO_SC_MCU_SUBSYS_CTRL5 (AO_CTRL_BASE + 0x414)
59#define AO_SC_MCU_SUBSYS_CTRL6 (AO_CTRL_BASE + 0x418)
60#define AO_SC_MCU_SUBSYS_CTRL7 (AO_CTRL_BASE + 0x41C)
61#define AO_SC_MCU_SUBSYS_STAT0 (AO_CTRL_BASE + 0x440)
62#define AO_SC_MCU_SUBSYS_STAT1 (AO_CTRL_BASE + 0x444)
63#define AO_SC_MCU_SUBSYS_STAT2 (AO_CTRL_BASE + 0x448)
64#define AO_SC_MCU_SUBSYS_STAT3 (AO_CTRL_BASE + 0x44C)
65#define AO_SC_MCU_SUBSYS_STAT4 (AO_CTRL_BASE + 0x450)
66#define AO_SC_MCU_SUBSYS_STAT5 (AO_CTRL_BASE + 0x454)
67#define AO_SC_MCU_SUBSYS_STAT6 (AO_CTRL_BASE + 0x458)
68#define AO_SC_MCU_SUBSYS_STAT7 (AO_CTRL_BASE + 0x45C)
69#define AO_SC_PERIPH_CLKEN4 (AO_CTRL_BASE + 0x630)
70#define AO_SC_PERIPH_CLKDIS4 (AO_CTRL_BASE + 0x634)
71#define AO_SC_PERIPH_CLKSTAT4 (AO_CTRL_BASE + 0x638)
72#define AO_SC_PERIPH_CLKEN5 (AO_CTRL_BASE + 0x63C)
73#define AO_SC_PERIPH_CLKDIS5 (AO_CTRL_BASE + 0x640)
74#define AO_SC_PERIPH_CLKSTAT5 (AO_CTRL_BASE + 0x644)
75#define AO_SC_PERIPH_RSTEN4 (AO_CTRL_BASE + 0x6F0)
76#define AO_SC_PERIPH_RSTDIS4 (AO_CTRL_BASE + 0x6F4)
77#define AO_SC_PERIPH_RSTSTAT4 (AO_CTRL_BASE + 0x6F8)
78#define AO_SC_PERIPH_RSTEN5 (AO_CTRL_BASE + 0x6FC)
79#define AO_SC_PERIPH_RSTDIS5 (AO_CTRL_BASE + 0x700)
80#define AO_SC_PERIPH_RSTSTAT5 (AO_CTRL_BASE + 0x704)
81#define AO_SC_PW_CLKEN0 (AO_CTRL_BASE + 0x800)
82#define AO_SC_PW_CLKDIS0 (AO_CTRL_BASE + 0x804)
83#define AO_SC_PW_CLK_STAT0 (AO_CTRL_BASE + 0x808)
84#define AO_SC_PW_RSTEN0 (AO_CTRL_BASE + 0x810)
85#define AO_SC_PW_RSTDIS0 (AO_CTRL_BASE + 0x814)
86#define AO_SC_PW_RST_STAT0 (AO_CTRL_BASE + 0x818)
87#define AO_SC_PW_ISOEN0 (AO_CTRL_BASE + 0x820)
88#define AO_SC_PW_ISODIS0 (AO_CTRL_BASE + 0x824)
89#define AO_SC_PW_ISO_STAT0 (AO_CTRL_BASE + 0x828)
90#define AO_SC_PW_MTCMOS_EN0 (AO_CTRL_BASE + 0x830)
91#define AO_SC_PW_MTCMOS_DIS0 (AO_CTRL_BASE + 0x834)
92#define AO_SC_PW_MTCMOS_STAT0 (AO_CTRL_BASE + 0x838)
93#define AO_SC_PW_MTCMOS_ACK_STAT0 (AO_CTRL_BASE + 0x83C)
94#define AO_SC_PW_MTCMOS_TIMEOUT_STAT0 (AO_CTRL_BASE + 0x840)
95#define AO_SC_PW_STAT0 (AO_CTRL_BASE + 0x850)
96#define AO_SC_PW_STAT1 (AO_CTRL_BASE + 0x854)
97#define AO_SC_SYSTEST_STAT (AO_CTRL_BASE + 0x880)
98#define AO_SC_SYSTEST_SLICER_CNT0 (AO_CTRL_BASE + 0x890)
99#define AO_SC_SYSTEST_SLICER_CNT1 (AO_CTRL_BASE + 0x894)
100#define AO_SC_PW_CTRL1 (AO_CTRL_BASE + 0x8C8)
101#define AO_SC_PW_CTRL (AO_CTRL_BASE + 0x8CC)
102#define AO_SC_MCPU_VOTEEN (AO_CTRL_BASE + 0x8D0)
103#define AO_SC_MCPU_VOTEDIS (AO_CTRL_BASE + 0x8D4)
104#define AO_SC_MCPU_VOTESTAT (AO_CTRL_BASE + 0x8D8)
105#define AO_SC_MCPU_VOTE_MSK0 (AO_CTRL_BASE + 0x8E0)
106#define AO_SC_MCPU_VOTE_MSK1 (AO_CTRL_BASE + 0x8E4)
107#define AO_SC_MCPU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x8E8)
108#define AO_SC_MCPU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x8EC)
109#define AO_SC_PERI_VOTEEN (AO_CTRL_BASE + 0x8F0)
110#define AO_SC_PERI_VOTEDIS (AO_CTRL_BASE + 0x8F4)
111#define AO_SC_PERI_VOTESTAT (AO_CTRL_BASE + 0x8F8)
112#define AO_SC_PERI_VOTE_MSK0 (AO_CTRL_BASE + 0x900)
113#define AO_SC_PERI_VOTE_MSK1 (AO_CTRL_BASE + 0x904)
114#define AO_SC_PERI_VOTESTAT0_MSK (AO_CTRL_BASE + 0x908)
115#define AO_SC_PERI_VOTESTAT1_MSK (AO_CTRL_BASE + 0x90C)
116#define AO_SC_ACPU_VOTEEN (AO_CTRL_BASE + 0x910)
117#define AO_SC_ACPU_VOTEDIS (AO_CTRL_BASE + 0x914)
118#define AO_SC_ACPU_VOTESTAT (AO_CTRL_BASE + 0x918)
119#define AO_SC_ACPU_VOTE_MSK0 (AO_CTRL_BASE + 0x920)
120#define AO_SC_ACPU_VOTE_MSK1 (AO_CTRL_BASE + 0x924)
121#define AO_SC_ACPU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x928)
122#define AO_SC_ACPU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x92C)
123#define AO_SC_MCU_VOTEEN (AO_CTRL_BASE + 0x930)
124#define AO_SC_MCU_VOTEDIS (AO_CTRL_BASE + 0x934)
125#define AO_SC_MCU_VOTESTAT (AO_CTRL_BASE + 0x938)
126#define AO_SC_MCU_VOTE_MSK0 (AO_CTRL_BASE + 0x940)
127#define AO_SC_MCU_VOTE_MSK1 (AO_CTRL_BASE + 0x944)
128#define AO_SC_MCU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x948)
129#define AO_SC_MCU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x94C)
130#define AO_SC_MCU_VOTE1EN (AO_CTRL_BASE + 0x960)
131#define AO_SC_MCU_VOTE1DIS (AO_CTRL_BASE + 0x964)
132#define AO_SC_MCU_VOTE1STAT (AO_CTRL_BASE + 0x968)
133#define AO_SC_MCU_VOTE1_MSK0 (AO_CTRL_BASE + 0x970)
134#define AO_SC_MCU_VOTE1_MSK1 (AO_CTRL_BASE + 0x974)
135#define AO_SC_MCU_VOTE1STAT0_MSK (AO_CTRL_BASE + 0x978)
136#define AO_SC_MCU_VOTE1STAT1_MSK (AO_CTRL_BASE + 0x97C)
137#define AO_SC_MCU_VOTE2EN (AO_CTRL_BASE + 0x980)
138#define AO_SC_MCU_VOTE2DIS (AO_CTRL_BASE + 0x984)
139#define AO_SC_MCU_VOTE2STAT (AO_CTRL_BASE + 0x988)
140#define AO_SC_MCU_VOTE2_MSK0 (AO_CTRL_BASE + 0x990)
141#define AO_SC_MCU_VOTE2_MSK1 (AO_CTRL_BASE + 0x994)
142#define AO_SC_MCU_VOTE2STAT0_MSK (AO_CTRL_BASE + 0x998)
143#define AO_SC_MCU_VOTE2STAT1_MSK (AO_CTRL_BASE + 0x99C)
144#define AO_SC_VOTE_CTRL (AO_CTRL_BASE + 0x9A0)
145#define AO_SC_VOTE_STAT (AO_CTRL_BASE + 0x9A4)
146#define AO_SC_ECONUM (AO_CTRL_BASE + 0xF00)
147#define AO_SCCHIPID (AO_CTRL_BASE + 0xF10)
148#define AO_SCSOCID (AO_CTRL_BASE + 0xF1C)
149#define AO_SC_SOC_FPGA_RTL_DEF (AO_CTRL_BASE + 0xFE0)
150#define AO_SC_SOC_FPGA_PR_DEF (AO_CTRL_BASE + 0xFE4)
151#define AO_SC_SOC_FPGA_RES_DEF0 (AO_CTRL_BASE + 0xFE8)
152#define AO_SC_SOC_FPGA_RES_DEF1 (AO_CTRL_BASE + 0xFEC)
153#define AO_SC_XTAL_CTRL0 (AO_CTRL_BASE + 0x102)
154#define AO_SC_XTAL_CTRL1 (AO_CTRL_BASE + 0x102)
155#define AO_SC_XTAL_CTRL3 (AO_CTRL_BASE + 0x103)
156#define AO_SC_XTAL_CTRL5 (AO_CTRL_BASE + 0x103)
157#define AO_SC_XTAL_STAT0 (AO_CTRL_BASE + 0x106)
158#define AO_SC_XTAL_STAT1 (AO_CTRL_BASE + 0x107)
159#define AO_SC_EFUSE_CHIPID0 (AO_CTRL_BASE + 0x108)
160#define AO_SC_EFUSE_CHIPID1 (AO_CTRL_BASE + 0x108)
161#define AO_SC_EFUSE_SYS_CTRL (AO_CTRL_BASE + 0x108)
162#define AO_SC_DEBUG_CTRL1 (AO_CTRL_BASE + 0x128)
163#define AO_SC_DBG_STAT (AO_CTRL_BASE + 0x12B)
164#define AO_SC_ARM_DBG_KEY0 (AO_CTRL_BASE + 0x12B)
165#define AO_SC_RESERVED31 (AO_CTRL_BASE + 0x13A)
166#define AO_SC_RESERVED32 (AO_CTRL_BASE + 0x13A)
167#define AO_SC_RESERVED33 (AO_CTRL_BASE + 0x13A)
168#define AO_SC_RESERVED34 (AO_CTRL_BASE + 0x13A)
169#define AO_SC_RESERVED35 (AO_CTRL_BASE + 0x13B)
170#define AO_SC_RESERVED36 (AO_CTRL_BASE + 0x13B)
171#define AO_SC_RESERVED37 (AO_CTRL_BASE + 0x13B)
172#define AO_SC_RESERVED38 (AO_CTRL_BASE + 0x13B)
173#define AO_SC_ALWAYSON_SYS_CTRL0 (AO_CTRL_BASE + 0x148)
174#define AO_SC_ALWAYSON_SYS_CTRL1 (AO_CTRL_BASE + 0x148)
175#define AO_SC_ALWAYSON_SYS_CTRL2 (AO_CTRL_BASE + 0x148)
176#define AO_SC_ALWAYSON_SYS_CTRL3 (AO_CTRL_BASE + 0x148)
177#define AO_SC_ALWAYSON_SYS_CTRL10 (AO_CTRL_BASE + 0x14A)
178#define AO_SC_ALWAYSON_SYS_CTRL11 (AO_CTRL_BASE + 0x14A)
179#define AO_SC_ALWAYSON_SYS_STAT0 (AO_CTRL_BASE + 0x14C)
180#define AO_SC_ALWAYSON_SYS_STAT1 (AO_CTRL_BASE + 0x14C)
181#define AO_SC_ALWAYSON_SYS_STAT2 (AO_CTRL_BASE + 0x14C)
182#define AO_SC_ALWAYSON_SYS_STAT3 (AO_CTRL_BASE + 0x14C)
183#define AO_SC_PWUP_TIME0 (AO_CTRL_BASE + 0x188)
184#define AO_SC_PWUP_TIME1 (AO_CTRL_BASE + 0x188)
185#define AO_SC_PWUP_TIME2 (AO_CTRL_BASE + 0x188)
186#define AO_SC_PWUP_TIME3 (AO_CTRL_BASE + 0x188)
187#define AO_SC_PWUP_TIME4 (AO_CTRL_BASE + 0x189)
188#define AO_SC_PWUP_TIME5 (AO_CTRL_BASE + 0x189)
189#define AO_SC_PWUP_TIME6 (AO_CTRL_BASE + 0x189)
190#define AO_SC_PWUP_TIME7 (AO_CTRL_BASE + 0x189)
191#define AO_SC_SECURITY_CTRL1 (AO_CTRL_BASE + 0x1C0)
192#define AO_SC_SYSTEST_SLICER_CNT0 (AO_CTRL_BASE + 0x890)
193#define AO_SC_SYSTEST_SLICER_CNT1 (AO_CTRL_BASE + 0x894)
194
195#define AO_SC_SYS_CTRL0_MODE_NORMAL 0x004
196#define AO_SC_SYS_CTRL0_MODE_MASK 0x007
197
198#define AO_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0)
199#define AO_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1)
200#define AO_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2)
201#define AO_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3)
202#define AO_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4)
203#define AO_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6)
204#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7)
205#define AO_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8)
206#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9)
207#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10)
208#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11)
209#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12)
210#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13)
211#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15)
212#define AO_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16)
213#define AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17)
214#define AO_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18)
215#define AO_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19)
216#define AO_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20)
217#define AO_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22)
218#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23)
219#define AO_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24)
220#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25)
221#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26)
222#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
223#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
224#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
225#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31)
226
227#define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
228#define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
229#define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
230#define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
231#define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
232#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31)
233
234#define AO_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
235#define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
236#define AO_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27)
237#define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
238#define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
239#define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
240#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31)
241
242#define AO_SC_SYS_STAT1_MODE_STATUS (1 << 0)
243#define AO_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
244#define AO_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17)
245#define AO_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19)
246#define AO_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20)
247#define AO_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27)
248#define AO_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28)
249#define AO_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29)
250
251#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_ECTR_N (1 << 0)
252#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_SYS_N (1 << 1)
253#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_POR_N (1 << 2)
254#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_DAP_N (1 << 3)
255#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_TIMER0_N (1 << 4)
256#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_TIMER1_N (1 << 5)
257#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_WDT0_N (1 << 6)
258#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_WDT1_N (1 << 7)
259#define AO_SC_PERIPH_RSTDIS4_HRESET_IPC_S_N (1 << 8)
260#define AO_SC_PERIPH_RSTDIS4_HRESET_IPC_NS_N (1 << 9)
261#define AO_SC_PERIPH_RSTDIS4_PRESET_EFUSEC_N (1 << 10)
262#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT0_N (1 << 12)
263#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT1_N (1 << 13)
264#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT2_N (1 << 14)
265#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER0_N (1 << 15)
266#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER1_N (1 << 16)
267#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER2_N (1 << 17)
268#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER3_N (1 << 18)
269#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER4_N (1 << 19)
270#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER5_N (1 << 20)
271#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER6_N (1 << 21)
272#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER7_N (1 << 22)
273#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER8_N (1 << 23)
274#define AO_SC_PERIPH_RSTDIS4_PRESET_UART0_N (1 << 24)
275#define AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N (1 << 25)
276#define AO_SC_PERIPH_RSTDIS4_RESET_RTC1_N (1 << 26)
277#define AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N (1 << 27)
278#define AO_SC_PERIPH_RSTDIS4_RESET_JTAG_AUTH_N (1 << 28)
279#define AO_SC_PERIPH_RSTDIS4_RESET_CS_DAPB_ON_N (1 << 29)
280#define AO_SC_PERIPH_RSTDIS4_MDM_SUBSYS_GLB (1 << 30)
281
282#define AO_SC_PERIPH_CLKEN4_HCLK_MCU (1 << 0)
283#define AO_SC_PERIPH_CLKEN4_CLK_MCU_DAP (1 << 3)
284#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_TIMER0 (1 << 4)
285#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_TIMER1 (1 << 5)
286#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_WDT0 (1 << 6)
287#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_WDT1 (1 << 7)
288#define AO_SC_PERIPH_CLKEN4_HCLK_IPC_S (1 << 8)
289#define AO_SC_PERIPH_CLKEN4_HCLK_IPC_NS (1 << 9)
290#define AO_SC_PERIPH_CLKEN4_PCLK_EFUSEC (1 << 10)
291#define AO_SC_PERIPH_CLKEN4_PCLK_TZPC (1 << 11)
292#define AO_SC_PERIPH_CLKEN4_PCLK_WDT0 (1 << 12)
293#define AO_SC_PERIPH_CLKEN4_PCLK_WDT1 (1 << 13)
294#define AO_SC_PERIPH_CLKEN4_PCLK_WDT2 (1 << 14)
295#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER0 (1 << 15)
296#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER1 (1 << 16)
297#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER2 (1 << 17)
298#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER3 (1 << 18)
299#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER4 (1 << 19)
300#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER5 (1 << 20)
301#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER6 (1 << 21)
302#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER7 (1 << 22)
303#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER8 (1 << 23)
304#define AO_SC_PERIPH_CLKEN4_CLK_UART0 (1 << 24)
305#define AO_SC_PERIPH_CLKEN4_CLK_RTC0 (1 << 25)
306#define AO_SC_PERIPH_CLKEN4_CLK_RTC1 (1 << 26)
307#define AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI (1 << 27)
308#define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH (1 << 28)
309#define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON (1 << 29)
310#define AO_SC_PERIPH_CLKEN4_CLK_PDM (1 << 30)
311#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1 << 31)
312
313#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU (1 << 0)
314#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU (1 << 1)
315#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_CCPU (1 << 2)
316#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_NS_CCPU (1 << 3)
317#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU (1 << 16)
318#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_MCU (1 << 17)
319#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_MCU (1 << 18)
320#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_NS_MCU (1 << 19)
321
322#define AO_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003
323#define AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007
324#define AO_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3)
325#define AO_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4)
326#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8)
327#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9)
328#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10)
329#define AO_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11)
330
331#define PCLK_TIMER1 (1 << 16)
332#define PCLK_TIMER0 (1 << 15)
333
334#endif /* __HI6220_AO_H__ */