| Varun Wadekar | eeeced5 | 2015-05-19 16:44:17 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __UART_16550_H__ |
| 32 | #define __UART_16550_H__ |
| 33 | |
| 34 | /* UART16550 Registers */ |
| 35 | #define UARTTX 0x0 |
| 36 | #define UARTRX 0x0 |
| 37 | #define UARTDLL 0x0 |
| 38 | #define UARTIER 0x4 |
| 39 | #define UARTDLLM 0x4 |
| 40 | #define UARTIIR 0x8 |
| 41 | #define UARTFCR 0x8 |
| 42 | #define UARTLCR 0xc |
| 43 | #define UARTMCR 0x10 |
| 44 | #define UARTLSR 0x14 |
| 45 | #define UARTMSR 0x18 |
| 46 | #define UARTSPR 0x1c |
| 47 | #define UARTCSR 0x20 |
| 48 | #define UARTRXFIFOCFG 0x24 |
| 49 | #define UARTMIE 0x28 |
| 50 | #define UARTVNDR 0x2c |
| 51 | #define UARTASR 0x3c |
| 52 | |
| 53 | /* FIFO Control Register bits */ |
| 54 | #define UARTFCR_FIFOMD_16450 (0 << 6) |
| 55 | #define UARTFCR_FIFOMD_16550 (1 << 6) |
| 56 | #define UARTFCR_RXTRIG_1 (0 << 6) |
| 57 | #define UARTFCR_RXTRIG_4 (1 << 6) |
| 58 | #define UARTFCR_RXTRIG_8 (2 << 6) |
| 59 | #define UARTFCR_RXTRIG_16 (3 << 6) |
| 60 | #define UARTFCR_TXTRIG_1 (0 << 4) |
| 61 | #define UARTFCR_TXTRIG_4 (1 << 4) |
| 62 | #define UARTFCR_TXTRIG_8 (2 << 4) |
| 63 | #define UARTFCR_TXTRIG_16 (3 << 4) |
| 64 | #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ |
| 65 | #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ |
| 66 | #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ |
| 67 | #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ |
| 68 | |
| 69 | /* Line Control Register bits */ |
| 70 | #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ |
| 71 | #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ |
| 72 | #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ |
| 73 | #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ |
| 74 | #define UARTLCR_PAR (1 << 3) /* Parity */ |
| 75 | #define UARTLCR_STOP (1 << 2) /* Stop Bit */ |
| 76 | #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ |
| 77 | #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ |
| 78 | #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ |
| 79 | #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ |
| 80 | |
| 81 | /* Line Status Register bits */ |
| 82 | #define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */ |
| 83 | #define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */ |
| 84 | #define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */ |
| 85 | #define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */ |
| 86 | #define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */ |
| 87 | #define UARTLSR_BRK (1 << 4) /* Break Condition Detected */ |
| 88 | #define UARTLSR_FERR (1 << 3) /* Framing Error */ |
| 89 | #define UARTLSR_PERR (1 << 3) /* Parity Error */ |
| 90 | #define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ |
| 91 | #define UARTLSR_RDR (1 << 2) /* Rx Data Ready */ |
| 92 | |
| 93 | #endif /* __UART_16550_H__ */ |