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Varun Wadekar7a9a2852015-09-18 11:21:22 +05301/*
Anthony Zhou59fd6152017-03-13 15:34:08 +08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar7a9a2852015-09-18 11:21:22 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar7a9a2852015-09-18 11:21:22 +05305 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef MEMCTRL_V1_H
8#define MEMCTRL_V1_H
Varun Wadekar7a9a2852015-09-18 11:21:22 +05309
10#include <mmio.h>
11#include <tegra_def.h>
12
13/* SMMU registers */
Anthony Zhou59fd6152017-03-13 15:34:08 +080014#define MC_SMMU_CONFIG_0 0x10U
15#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U
16#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U
17#define MC_SMMU_TLB_CONFIG_0 0x14U
18#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U
19#define MC_SMMU_PTC_CONFIG_0 0x18U
20#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU
21#define MC_SMMU_TLB_FLUSH_0 0x30U
22#define TLB_FLUSH_VA_MATCH_ALL 0U
23#define TLB_FLUSH_ASID_MATCH_DISABLE 0U
24#define TLB_FLUSH_ASID_MATCH_SHIFT 31U
Varun Wadekar7a9a2852015-09-18 11:21:22 +053025#define MC_SMMU_TLB_FLUSH_ALL \
26 (TLB_FLUSH_VA_MATCH_ALL | \
27 (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
Anthony Zhou59fd6152017-03-13 15:34:08 +080028#define MC_SMMU_PTC_FLUSH_0 0x34U
29#define MC_SMMU_PTC_FLUSH_ALL 0U
30#define MC_SMMU_ASID_SECURITY_0 0x38U
31#define MC_SMMU_ASID_SECURITY 0U
32#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U
33#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU
34#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U
35#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U
36#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U
Varun Wadekar7a9a2852015-09-18 11:21:22 +053037#define MC_SMMU_TRANSLATION_ENABLE (~0)
38
Varun Wadekarc92050b2017-03-29 14:57:29 -070039/* MC IRAM aperture registers */
40#define MC_IRAM_BASE_LO 0x65CU
41#define MC_IRAM_TOP_LO 0x660U
42#define MC_IRAM_BASE_TOP_HI 0x980U
43#define MC_IRAM_REG_CTRL 0x964U
44#define MC_DISABLE_IRAM_CFG_WRITES 1U
45
Varun Wadekar7a9a2852015-09-18 11:21:22 +053046static inline uint32_t tegra_mc_read_32(uint32_t off)
47{
48 return mmio_read_32(TEGRA_MC_BASE + off);
49}
50
51static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
52{
53 mmio_write_32(TEGRA_MC_BASE + off, val);
54}
55
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000056#endif /* MEMCTRL_V1_H */