| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame^] | 7 | #ifndef CORTEX_A35_H |
| 8 | #define CORTEX_A35_H |
| Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 9 | |
| 10 | /* Cortex-A35 Main ID register for revision 0 */ |
| 11 | #define CORTEX_A35_MIDR 0x410FD040 |
| 12 | |
| 13 | /******************************************************************************* |
| 14 | * CPU Extended Control register specific definitions. |
| 15 | * CPUECTLR_EL1 is an implementation-specific register. |
| 16 | ******************************************************************************/ |
| 17 | #define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 |
| 18 | #define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6) |
| 19 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame^] | 20 | #endif /* CORTEX_A35_H */ |