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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
7#ifndef __PLAT_PRIVATE_H__
8#define __PLAT_PRIVATE_H__
9
10#ifndef __ASSEMBLY__
11#include <mmio.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010012#include <psci.h>
Tony Xief6118cc2016-01-15 17:17:32 +080013#include <stdint.h>
14#include <xlat_tables.h>
15
Caesar Wangd90f43e2016-10-11 09:36:00 +080016#define __sramdata __attribute__((section(".sram.data")))
17#define __sramconst __attribute__((section(".sram.rodata")))
Lin Huang30e43392017-05-04 16:02:45 +080018#define __sramfunc __attribute__((section(".sram.text")))
19
20#define __pmusramdata __attribute__((section(".pmusram.data")))
21#define __pmusramconst __attribute__((section(".pmusram.rodata")))
22#define __pmusramfunc __attribute__((section(".pmusram.text")))
Caesar Wangd90f43e2016-10-11 09:36:00 +080023
24extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
25extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
Lin Huang30e43392017-05-04 16:02:45 +080026extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
Lin Huang88dd1232017-05-16 16:40:46 +080027extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
Xing Zheng93280b72016-10-26 21:25:26 +080028extern uint32_t __sram_incbin_start, __sram_incbin_end;
Lin Huang88dd1232017-05-16 16:40:46 +080029extern uint32_t __sram_incbin_real_end;
Caesar Wangd90f43e2016-10-11 09:36:00 +080030
Antonio Nino Diaz58230902018-09-24 17:16:20 +010031struct rockchip_bl31_params {
32 param_header_t h;
33 image_info_t *bl31_image_info;
34 entry_point_info_t *bl32_ep_info;
35 image_info_t *bl32_image_info;
36 entry_point_info_t *bl33_ep_info;
37 image_info_t *bl33_image_info;
38};
Tony Xief6118cc2016-01-15 17:17:32 +080039
40/******************************************************************************
41 * The register have write-mask bits, it is mean, if you want to set the bits,
42 * you needs set the write-mask bits at the same time,
43 * The write-mask bits is in high 16-bits.
44 * The fllowing macro definition helps access write-mask bits reg efficient!
45 ******************************************************************************/
46#define REG_MSK_SHIFT 16
47
Tony Xief6118cc2016-01-15 17:17:32 +080048#ifndef WMSK_BIT
49#define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT)
50#endif
51
52/* set one bit with write mask */
53#ifndef BIT_WITH_WMSK
54#define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
55#endif
56
57#ifndef BITS_SHIFT
58#define BITS_SHIFT(bits, shift) (bits << (shift))
59#endif
60
61#ifndef BITS_WITH_WMASK
Caesar Wang59e41b52016-04-10 14:11:07 +080062#define BITS_WITH_WMASK(bits, msk, shift)\
Tony Xief6118cc2016-01-15 17:17:32 +080063 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
64#endif
65
66/******************************************************************************
67 * Function and variable prototypes
68 *****************************************************************************/
69void plat_configure_mmu_el3(unsigned long total_base,
70 unsigned long total_size,
71 unsigned long,
72 unsigned long,
73 unsigned long,
74 unsigned long);
75
76void plat_cci_init(void);
77void plat_cci_enable(void);
78void plat_cci_disable(void);
79
80void plat_delay_timer_init(void);
81
Caesar Wang3e3c5b02016-05-25 19:03:04 +080082void params_early_setup(void *plat_params_from_bl2);
83
Tony Xief6118cc2016-01-15 17:17:32 +080084void plat_rockchip_gic_driver_init(void);
85void plat_rockchip_gic_init(void);
86void plat_rockchip_gic_cpuif_enable(void);
87void plat_rockchip_gic_cpuif_disable(void);
88void plat_rockchip_gic_pcpu_init(void);
89
Tony Xief6118cc2016-01-15 17:17:32 +080090void plat_rockchip_pmu_init(void);
91void plat_rockchip_soc_init(void);
Tony Xie42e113e2016-07-16 11:16:51 +080092uintptr_t plat_get_sec_entrypoint(void);
Tony Xief6118cc2016-01-15 17:17:32 +080093
Caesar Wang59e41b52016-04-10 14:11:07 +080094void platform_cpu_warmboot(void);
95
Caesar Wangef180072016-09-10 02:43:15 +080096struct gpio_info *plat_get_rockchip_gpio_reset(void);
97struct gpio_info *plat_get_rockchip_gpio_poweroff(void);
98struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
Caesar Wang5045a1c2016-09-10 02:47:53 +080099struct apio_info *plat_get_rockchip_suspend_apio(void);
Caesar Wang038f6aa2016-05-25 19:21:43 +0800100void plat_rockchip_gpio_init(void);
Lin Huang2c60b5f2017-05-18 18:04:25 +0800101void plat_rockchip_save_gpio(void);
102void plat_rockchip_restore_gpio(void);
Caesar Wang038f6aa2016-05-25 19:21:43 +0800103
tony.xie422d51c2017-03-01 11:05:17 +0800104int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
105int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
106 plat_local_state_t lvl_state);
107int rockchip_soc_cores_pwr_dm_off(void);
108int rockchip_soc_sys_pwr_dm_suspend(void);
109int rockchip_soc_cores_pwr_dm_suspend(void);
110int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
111 plat_local_state_t lvl_state);
112int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
113 plat_local_state_t lvl_state);
114int rockchip_soc_cores_pwr_dm_on_finish(void);
115int rockchip_soc_sys_pwr_dm_resume(void);
116
117int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
118 plat_local_state_t lvl_state);
119int rockchip_soc_cores_pwr_dm_resume(void);
120void __dead2 rockchip_soc_soft_reset(void);
121void __dead2 rockchip_soc_system_off(void);
122void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
123 const psci_power_state_t *target_state);
124void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
125
Tony Xief6118cc2016-01-15 17:17:32 +0800126extern const unsigned char rockchip_power_domain_tree_desc[];
127
Lin Huang30e43392017-05-04 16:02:45 +0800128extern void *pmu_cpuson_entrypoint;
Tony Xief6118cc2016-01-15 17:17:32 +0800129extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT];
130extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
131
132extern const mmap_region_t plat_rk_mmap[];
Caesar Wangd90f43e2016-10-11 09:36:00 +0800133
Lin Huang30e43392017-05-04 16:02:45 +0800134void rockchip_plat_mmu_el3(void);
Caesar Wangd90f43e2016-10-11 09:36:00 +0800135
Tony Xief6118cc2016-01-15 17:17:32 +0800136#endif /* __ASSEMBLY__ */
137
Tony Xie42e113e2016-07-16 11:16:51 +0800138/******************************************************************************
139 * cpu up status
140 * The bits of macro value is not more than 12 bits for cmp instruction!
141 ******************************************************************************/
142#define PMU_CPU_HOTPLUG 0xf00
143#define PMU_CPU_AUTO_PWRDN 0xf0
144#define PMU_CLST_RET 0xa5
Tony Xief6118cc2016-01-15 17:17:32 +0800145
146#endif /* __PLAT_PRIVATE_H__ */