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Michael Brandlafdff3c2018-02-22 16:30:30 +01001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __HIKEY_LAYOUT_H
8#define __HIKEY_LAYOUT_H
9
10/*
11 * Platform memory map related constants
12 */
13#define XG2RAM0_BASE 0xF9800000
14#define XG2RAM0_SIZE 0x00400000
15
16/*
17 * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
18 */
19#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
20#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
21#define BL1_XG2RAM0_OFFSET 0x1000
22
23/*
24 * BL1 specific defines.
25 *
26 * Both loader and BL1_RO region stay in SRAM since they are used to simulate
27 * ROM.
28 * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
29 *
30 * ++++++++++ 0xF980_0000
31 * + loader +
32 * ++++++++++ 0xF980_1000
33 * + BL1_RO +
Haojian Zhuangc104f192018-07-18 17:07:00 +080034 * ++++++++++ 0xF981_8000
Michael Brandlafdff3c2018-02-22 16:30:30 +010035 * + BL1_RW +
36 * ++++++++++ 0xF989_8000
37 */
38#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
Haojian Zhuangc104f192018-07-18 17:07:00 +080039#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x18000)
40#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_8000 */
41#define BL1_RW_SIZE (0x00080000)
Michael Brandlafdff3c2018-02-22 16:30:30 +010042#define BL1_RW_LIMIT (0xF9898000)
43
44/*
45 * Non-Secure BL1U specific defines.
46 */
Haojian Zhuangc104f192018-07-18 17:07:00 +080047#define NS_BL1U_BASE (0xf9828000)
Michael Brandlafdff3c2018-02-22 16:30:30 +010048#define NS_BL1U_SIZE (0x00010000)
49#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
50
51/*
52 * BL2 specific defines.
53 *
54 * Both loader and BL2 region stay in SRAM.
55 * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
56 *
57 * ++++++++++ 0xF980_0000
58 * + loader +
59 * ++++++++++ 0xF980_1000
60 * + BL2 +
Teddy Reed349cf892018-06-22 22:23:36 -040061 * ++++++++++ 0xF983_0000
Michael Brandlafdff3c2018-02-22 16:30:30 +010062 */
63#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
Teddy Reed349cf892018-06-22 22:23:36 -040064#define BL2_LIMIT (0xF9830000) /* 0xf983_0000 */
Michael Brandlafdff3c2018-02-22 16:30:30 +010065
66/*
67 * SCP_BL2 specific defines.
68 * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
69 * at 0x0100_0000. Then BL2 will parse the sections and loaded them into
70 * predefined separated buffers.
71 */
72#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
73#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
74#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
75
76/*
77 * BL31 specific defines.
78 */
79#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
80#define BL31_LIMIT (0xF9898000)
81
82/*
83 * BL3-2 specific defines.
84 */
85
86/*
87 * The TSP currently executes from TZC secured area of DRAM or SRAM.
88 */
89#define BL32_SRAM_BASE BL31_LIMIT
90#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
91
92#define BL32_DRAM_BASE DDR_SEC_BASE
93#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
94
95#ifdef SPD_opteed
96/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
97#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
98#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
99#endif
100
101#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
102#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
103#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
104#define BL32_BASE BL32_DRAM_BASE
105#define BL32_LIMIT BL32_DRAM_LIMIT
106#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
107#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
108#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
109#define BL32_BASE BL32_SRAM_BASE
110#define BL32_LIMIT BL32_SRAM_LIMIT
111#else
112#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
113#endif
114
115/* BL32 is mandatory in AArch32 */
116#ifndef AARCH32
117#ifdef SPD_none
118#undef BL32_BASE
119#endif /* SPD_none */
120#endif
121
122#endif /* !__HIKEY_LAYOUT_H */