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Joel Huttona7c46872018-01-10 16:06:07 +00001/*
John Tsichritzis16e6d9f2019-02-19 14:01:55 +00002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Joel Huttona7c46872018-01-10 16:06:07 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <arch.h>
7#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/bl_common.h>
9#include <common/debug.h>
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000010#include <neoverse_e1.h>
Joel Huttona7c46872018-01-10 16:06:07 +000011#include <cpu_macros.S>
Joel Huttona7c46872018-01-10 16:06:07 +000012#include <plat_macros.S>
13
John Tsichritzisfe6df392019-03-19 17:20:52 +000014/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
John Tsichritzis7557c662019-06-03 13:54:30 +010019/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000024func neoverse_e1_cpu_pwr_dwn
25 mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
26 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
27 msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0
Joel Huttona7c46872018-01-10 16:06:07 +000028 isb
29 ret
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000030endfunc neoverse_e1_cpu_pwr_dwn
Joel Huttona7c46872018-01-10 16:06:07 +000031
Soby Mathew0980dce2018-09-17 04:34:35 +010032#if REPORT_ERRATA
33/*
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000034 * Errata printing function for Neoverse N1. Must follow AAPCS.
Soby Mathew0980dce2018-09-17 04:34:35 +010035 */
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000036func neoverse_e1_errata_report
Soby Mathew0980dce2018-09-17 04:34:35 +010037 ret
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000038endfunc neoverse_e1_errata_report
Soby Mathew0980dce2018-09-17 04:34:35 +010039#endif
40
41
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000042.section .rodata.neoverse_e1_regs, "aS"
43neoverse_e1_regs: /* The ascii list of register names to be reported */
Joel Huttona7c46872018-01-10 16:06:07 +000044 .asciz "cpuectlr_el1", ""
45
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000046func neoverse_e1_cpu_reg_dump
47 adr x6, neoverse_e1_regs
48 mrs x8, NEOVERSE_E1_ECTLR_EL1
Joel Huttona7c46872018-01-10 16:06:07 +000049 ret
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000050endfunc neoverse_e1_cpu_reg_dump
Joel Huttona7c46872018-01-10 16:06:07 +000051
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000052declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \
Joel Huttona7c46872018-01-10 16:06:07 +000053 CPU_NO_RESET_FUNC, \
John Tsichritzis16e6d9f2019-02-19 14:01:55 +000054 neoverse_e1_cpu_pwr_dwn