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git01.mediatek.com / filogic / atf / 5e890b368406fb5b765bb93afed6e460c16ba21a / . / plat / nvidia / tegra / soc / t194 / plat_sip_calls.c
blob: cb57c9b6160f4d057755b48053ddb72194b5f311 [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]1/*
2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
10#include <common/bl_common.h>
11#include <lib/el3_runtime/context_mgmt.h>
12#include <common/debug.h>
13#include <errno.h>
14#include <mce.h>
15#include <memctrl.h>
16#include <common/runtime_svc.h>
17#include <tegra_private.h>
18
19extern uint32_t tegra186_system_powerdn_state;
20
21/*******************************************************************************
22 * Tegra186 SiP SMCs
23 ******************************************************************************/
Varun Wadekar221093b2017-02-22 11:57:15 -0800[diff] [blame]24#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01
25#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02
26#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00
27#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01
28#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02
29#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
30#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
31#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
32#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
33#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
34#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
35#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
36#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A
37#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B
38#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C
39#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D
40#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E
41#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F
42#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10
43#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11
44#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]45
46/*******************************************************************************
47 * This function is responsible for handling all T186 SiP calls
48 ******************************************************************************/
49int plat_sip_handler(uint32_t smc_fid,
50 uint64_t x1,
51 uint64_t x2,
52 uint64_t x3,
53 uint64_t x4,
54 void *cookie,
55 void *handle,
56 uint64_t flags)
57{
58 int mce_ret;
59
Varun Wadekar221093b2017-02-22 11:57:15 -0800[diff] [blame]60 /*
61 * Convert SMC FID to SMC64 until the linux driver uses
62 * SMC64 encoding.
63 */
64 smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
65
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]66 switch (smc_fid) {
67
68 /*
69 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
70 * 0x82FFFFFF SiP SMC space
71 */
72 case TEGRA_SIP_MCE_CMD_ENTER_CSTATE:
73 case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO:
74 case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME:
75 case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS:
76 case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS:
77 case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED:
78 case TEGRA_SIP_MCE_CMD_CC3_CTRL:
79 case TEGRA_SIP_MCE_CMD_ECHO_DATA:
80 case TEGRA_SIP_MCE_CMD_READ_VERSIONS:
81 case TEGRA_SIP_MCE_CMD_ENUM_FEATURES:
82 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
83 case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA:
84 case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
85 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
86 case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
87 case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
88 case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ:
89 case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
90
91 /* clean up the high bits */
92 smc_fid &= MCE_CMD_MASK;
93
94 /* execute the command and store the result */
95 mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
96 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret);
97
98 return 0;
99
100 case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE:
101
102 /* clean up the high bits */
103 x1 = (uint32_t)x1;
104
105 /*
106 * SC8 is a special Tegra186 system state where the CPUs and
107 * DRAM are powered down but the other subsystem is still
108 * alive.
109 */
110
111 return 0;
112
113 default:
114 break;
115 }
116
117 return -ENOTSUP;
118}