blob: a9e86ef64a9a271590e4abb407d26a82e1d9977c [file] [log] [blame]
Etienne Carrierea1249e02017-11-05 22:56:19 +01001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CORTEX_A9_H
8#define CORTEX_A9_H
Etienne Carrierea1249e02017-11-05 22:56:19 +01009
10/*******************************************************************************
11 * Cortex-A9 midr with version/revision set to 0
12 ******************************************************************************/
13#define CORTEX_A9_MIDR 0x410FC090
14
15/*******************************************************************************
16 * CPU Auxiliary Control register specific definitions.
17 ******************************************************************************/
18#define CORTEX_A9_ACTLR_SMP_BIT (1 << 6)
19#define CORTEX_A9_ACTLR_FLZW_BIT (1 << 3)
20
21/*******************************************************************************
22 * CPU Power Control Register
23 ******************************************************************************/
24#define PCR p15, 0, c15, c0, 0
25
26#ifndef __ASSEMBLY__
27#include <arch_helpers.h>
28DEFINE_COPROCR_RW_FUNCS(pcr, PCR)
29#endif
30
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000031#endif /* CORTEX_A9_H */