Govindraj Raja | 37012fb | 2023-06-23 11:28:05 -0500 | [diff] [blame] | 1 | /* |
Bipin Ravi | 38ab0b7 | 2024-03-12 10:29:16 -0500 | [diff] [blame] | 2 | * Copyright (c) 2021-2024, Arm Limited. All rights reserved. |
Govindraj Raja | 37012fb | 2023-06-23 11:28:05 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a720.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
| 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
| 17 | #error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 22 | #error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 23 | #endif |
| 24 | |
| 25 | #if WORKAROUND_CVE_2022_23960 |
| 26 | wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 |
| 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
Bipin Ravi | 5e03975 | 2024-03-14 16:52:21 -0500 | [diff] [blame^] | 29 | workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 |
| 30 | /* Erratum 2926083 workaround is required only if SPE is enabled */ |
| 31 | #if ENABLE_SPE_FOR_NS != 0 |
| 32 | /* Check if Static profiling extension is implemented or present. */ |
| 33 | mrs x1, id_aa64dfr0_el1 |
| 34 | ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 |
| 35 | cbz x0, 1f |
| 36 | /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ |
| 37 | sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57) |
| 38 | sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58) |
| 39 | 1: |
| 40 | #endif |
| 41 | workaround_reset_end cortex_a720, ERRATUM(2926083) |
| 42 | |
| 43 | check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) |
| 44 | |
Bipin Ravi | 38ab0b7 | 2024-03-12 10:29:16 -0500 | [diff] [blame] | 45 | workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 |
| 46 | sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) |
| 47 | workaround_reset_end cortex_a720, ERRATUM(2940794) |
| 48 | |
| 49 | check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) |
| 50 | |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 51 | workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 52 | #if IMAGE_BL31 |
Govindraj Raja | 37012fb | 2023-06-23 11:28:05 -0500 | [diff] [blame] | 53 | /* |
| 54 | * The Cortex A720 generic vectors are overridden to apply errata |
| 55 | * mitigation on exception entry from lower ELs. |
| 56 | */ |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 57 | override_vector_table wa_cve_vbar_cortex_a720 |
| 58 | #endif /* IMAGE_BL31 */ |
| 59 | workaround_reset_end cortex_a720, CVE(2022, 23960) |
Govindraj Raja | 37012fb | 2023-06-23 11:28:05 -0500 | [diff] [blame] | 60 | |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 61 | check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 62 | |
| 63 | cpu_reset_func_start cortex_a720 |
| 64 | /* Disable speculative loads */ |
| 65 | msr SSBS, xzr |
| 66 | cpu_reset_func_end cortex_a720 |
Govindraj Raja | 37012fb | 2023-06-23 11:28:05 -0500 | [diff] [blame] | 67 | |
| 68 | /* ---------------------------------------------------- |
| 69 | * HW will do the cache maintenance while powering down |
| 70 | * ---------------------------------------------------- |
| 71 | */ |
| 72 | func cortex_a720_core_pwr_dwn |
| 73 | /* --------------------------------------------------- |
| 74 | * Enable CPU power down bit in power control register |
| 75 | * --------------------------------------------------- |
| 76 | */ |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 77 | sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 78 | |
Govindraj Raja | 37012fb | 2023-06-23 11:28:05 -0500 | [diff] [blame] | 79 | isb |
| 80 | ret |
| 81 | endfunc cortex_a720_core_pwr_dwn |
| 82 | |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 83 | errata_report_shim cortex_a720 |
Govindraj Raja | 37012fb | 2023-06-23 11:28:05 -0500 | [diff] [blame] | 84 | |
| 85 | /* --------------------------------------------- |
| 86 | * This function provides Cortex A720-specific |
| 87 | * register information for crash reporting. |
| 88 | * It needs to return with x6 pointing to |
| 89 | * a list of register names in ascii and |
| 90 | * x8 - x15 having values of registers to be |
| 91 | * reported. |
| 92 | * --------------------------------------------- |
| 93 | */ |
| 94 | .section .rodata.cortex_a720_regs, "aS" |
| 95 | cortex_a720_regs: /* The ascii list of register names to be reported */ |
| 96 | .asciz "cpuectlr_el1", "" |
| 97 | |
| 98 | func cortex_a720_cpu_reg_dump |
| 99 | adr x6, cortex_a720_regs |
| 100 | mrs x8, CORTEX_A720_CPUECTLR_EL1 |
| 101 | ret |
| 102 | endfunc cortex_a720_cpu_reg_dump |
| 103 | |
| 104 | declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ |
| 105 | cortex_a720_reset_func, \ |
| 106 | cortex_a720_core_pwr_dwn |