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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Summer Qin93c812f2017-02-28 16:46:17 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Dan Handley9df48042015-03-19 18:58:55 +00009#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
Soby Mathewfec4eb72015-07-01 16:16:20 +010011#include <plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +000012
Soby Mathewfec4eb72015-07-01 16:16:20 +010013/*******************************************************************************
14 * This function validates an MPIDR by checking whether it falls within the
15 * acceptable bounds. An error code (-1) is returned if an incorrect mpidr
16 * is passed.
17 ******************************************************************************/
18int arm_check_mpidr(u_register_t mpidr)
Dan Handley9df48042015-03-19 18:58:55 +000019{
Soby Mathewfec4eb72015-07-01 16:16:20 +010020 unsigned int cluster_id, cpu_id;
Summer Qin93c812f2017-02-28 16:46:17 +000021 uint64_t valid_mask;
Soby Mathewfec4eb72015-07-01 16:16:20 +010022
Summer Qin93c812f2017-02-28 16:46:17 +000023#if ARM_PLAT_MT
24 unsigned int pe_id;
Soby Mathewfec4eb72015-07-01 16:16:20 +010025
Summer Qin93c812f2017-02-28 16:46:17 +000026 valid_mask = ~(MPIDR_AFFLVL_MASK |
27 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) |
28 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT));
29 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
30 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
31 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
32#else
33 valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK);
Sathees Balya30952cc2018-09-27 14:41:02 +010034 cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) &
35 MPIDR_AFFLVL_MASK);
36 cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) &
37 MPIDR_AFFLVL_MASK);
Summer Qin93c812f2017-02-28 16:46:17 +000038#endif /* ARM_PLAT_MT */
39
40 mpidr &= MPIDR_AFFINITY_MASK;
Sathees Balya30952cc2018-09-27 14:41:02 +010041 if ((mpidr & valid_mask) != 0U)
Summer Qin93c812f2017-02-28 16:46:17 +000042 return -1;
Soby Mathewfec4eb72015-07-01 16:16:20 +010043
Soby Mathew47e43f22016-02-01 14:04:34 +000044 if (cluster_id >= PLAT_ARM_CLUSTER_COUNT)
Soby Mathewfec4eb72015-07-01 16:16:20 +010045 return -1;
46
47 /* Validate cpu_id by checking whether it represents a CPU in
48 one of the two clusters present on the platform. */
Soby Mathew47e43f22016-02-01 14:04:34 +000049 if (cpu_id >= plat_arm_get_cluster_core_count(mpidr))
Soby Mathewfec4eb72015-07-01 16:16:20 +010050 return -1;
51
Summer Qin93c812f2017-02-28 16:46:17 +000052#if ARM_PLAT_MT
53 if (pe_id >= plat_arm_get_cpu_pe_count(mpidr))
54 return -1;
55#endif /* ARM_PLAT_MT */
56
Soby Mathewfec4eb72015-07-01 16:16:20 +010057 return 0;
Dan Handley9df48042015-03-19 18:58:55 +000058}