Ying-Chun Liu (PaulLiu) | 7eee8ef | 2019-01-30 04:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, Linaro Limited |
| 3 | * Copyright (c) 2019, Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef RPI3_SDHOST_H |
| 9 | #define RPI3_SDHOST_H |
| 10 | |
| 11 | #include <drivers/mmc.h> |
| 12 | #include <stdint.h> |
| 13 | #include <platform_def.h> |
| 14 | |
| 15 | struct rpi3_sdhost_params { |
| 16 | uintptr_t reg_base; |
| 17 | uint32_t clk_rate; |
Rob Newberry | 5db3008 | 2023-03-30 10:43:21 -0700 | [diff] [blame^] | 18 | uint32_t clk_rate_initial; |
Ying-Chun Liu (PaulLiu) | 7eee8ef | 2019-01-30 04:17:32 +0800 | [diff] [blame] | 19 | uint32_t bus_width; |
| 20 | uint32_t flags; |
| 21 | uint32_t current_cmd; |
| 22 | uint8_t cmdbusy; |
| 23 | uint8_t mmc_app_cmd; |
| 24 | uint32_t ns_per_fifo_word; |
Ying-Chun Liu (PaulLiu) | 7eee8ef | 2019-01-30 04:17:32 +0800 | [diff] [blame] | 25 | |
| 26 | uint32_t sdcard_rca; |
| 27 | uint32_t gpio48_pinselect[6]; |
| 28 | }; |
| 29 | |
| 30 | void rpi3_sdhost_init(struct rpi3_sdhost_params *params, |
| 31 | struct mmc_device_info *mmc_dev_info); |
| 32 | void rpi3_sdhost_stop(void); |
| 33 | |
| 34 | /* Registers */ |
| 35 | #define HC_COMMAND 0x00 /* Command and flags */ |
| 36 | #define HC_ARGUMENT 0x04 |
| 37 | #define HC_TIMEOUTCOUNTER 0x08 |
| 38 | #define HC_CLOCKDIVISOR 0x0c |
| 39 | #define HC_RESPONSE_0 0x10 |
| 40 | #define HC_RESPONSE_1 0x14 |
| 41 | #define HC_RESPONSE_2 0x18 |
| 42 | #define HC_RESPONSE_3 0x1c |
| 43 | #define HC_HOSTSTATUS 0x20 |
| 44 | #define HC_POWER 0x30 |
| 45 | #define HC_DEBUG 0x34 |
| 46 | #define HC_HOSTCONFIG 0x38 |
| 47 | #define HC_BLOCKSIZE 0x3c |
| 48 | #define HC_DATAPORT 0x40 |
| 49 | #define HC_BLOCKCOUNT 0x50 |
| 50 | |
| 51 | /* Flags for HC_COMMAND register */ |
| 52 | #define HC_CMD_ENABLE 0x8000 |
| 53 | #define HC_CMD_FAILED 0x4000 |
| 54 | #define HC_CMD_BUSY 0x0800 |
| 55 | #define HC_CMD_RESPONSE_NONE 0x0400 |
| 56 | #define HC_CMD_RESPONSE_LONG 0x0200 |
| 57 | #define HC_CMD_WRITE 0x0080 |
| 58 | #define HC_CMD_READ 0x0040 |
| 59 | #define HC_CMD_COMMAND_MASK 0x003f |
| 60 | |
Rob Newberry | 5db3008 | 2023-03-30 10:43:21 -0700 | [diff] [blame^] | 61 | #define RPI3_SDHOST_MAX_CLOCK 250000000 // technically, we should obtain this number from the mailbox |
| 62 | |
Ying-Chun Liu (PaulLiu) | 7eee8ef | 2019-01-30 04:17:32 +0800 | [diff] [blame] | 63 | #define HC_CLOCKDIVISOR_MAXVAL 0x07ff |
| 64 | #define HC_CLOCKDIVISOR_PREFERVAL 0x027b |
| 65 | #define HC_CLOCKDIVISOR_SLOWVAL 0x0148 |
| 66 | #define HC_CLOCKDIVISOR_STOPVAL 0x01fb |
| 67 | |
| 68 | /* Flags for HC_HOSTSTATUS register */ |
| 69 | #define HC_HSTST_HAVEDATA 0x0001 |
| 70 | #define HC_HSTST_ERROR_FIFO 0x0008 |
| 71 | #define HC_HSTST_ERROR_CRC7 0x0010 |
| 72 | #define HC_HSTST_ERROR_CRC16 0x0020 |
| 73 | #define HC_HSTST_TIMEOUT_CMD 0x0040 |
| 74 | #define HC_HSTST_TIMEOUT_DATA 0x0080 |
| 75 | #define HC_HSTST_INT_BLOCK 0x0200 |
| 76 | #define HC_HSTST_INT_BUSY 0x0400 |
| 77 | |
| 78 | #define HC_HSTST_RESET 0xffff |
| 79 | |
| 80 | #define HC_HSTST_MASK_ERROR_DATA (HC_HSTST_ERROR_FIFO | \ |
| 81 | HC_HSTST_ERROR_CRC7 | \ |
| 82 | HC_HSTST_ERROR_CRC16 | \ |
| 83 | HC_HSTST_TIMEOUT_DATA) |
| 84 | |
| 85 | #define HC_HSTST_MASK_ERROR_ALL (HC_HSTST_MASK_ERROR_DATA | \ |
| 86 | HC_HSTST_TIMEOUT_CMD) |
| 87 | |
| 88 | /* Flags for HC_HOSTCONFIG register */ |
| 89 | #define HC_HSTCF_INTBUS_WIDE 0x0002 |
| 90 | #define HC_HSTCF_EXTBUS_4BIT 0x0004 |
| 91 | #define HC_HSTCF_SLOW_CARD 0x0008 |
| 92 | #define HC_HSTCF_INT_DATA 0x0010 |
| 93 | #define HC_HSTCF_INT_BLOCK 0x0100 |
| 94 | #define HC_HSTCF_INT_BUSY 0x0400 |
| 95 | |
| 96 | /* Flags for HC_DEBUG register */ |
| 97 | #define HC_DBG_FIFO_THRESH_WRITE_SHIFT 9 |
| 98 | #define HC_DBG_FIFO_THRESH_READ_SHIFT 14 |
| 99 | #define HC_DBG_FIFO_THRESH_MASK 0x001f |
| 100 | #define HC_DBG_FSM_MASK 0xf |
| 101 | #define HC_DBG_FSM_IDENTMODE 0x0 |
| 102 | #define HC_DBG_FSM_DATAMODE 0x1 |
| 103 | #define HC_DBG_FSM_READDATA 0x2 |
| 104 | #define HC_DBG_FSM_WRITEDATA 0x3 |
| 105 | #define HC_DBG_FSM_READWAIT 0x4 |
| 106 | #define HC_DBG_FSM_READCRC 0x5 |
| 107 | #define HC_DBG_FSM_WRITECRC 0x6 |
| 108 | #define HC_DBG_FSM_WRITEWAIT1 0x7 |
| 109 | #define HC_DBG_FSM_POWERDOWN 0x8 |
| 110 | #define HC_DBG_FSM_POWERUP 0x9 |
| 111 | #define HC_DBG_FSM_WRITESTART1 0xa |
| 112 | #define HC_DBG_FSM_WRITESTART2 0xb |
| 113 | #define HC_DBG_FSM_GENPULSES 0xc |
| 114 | #define HC_DBG_FSM_WRITEWAIT2 0xd |
| 115 | #define HC_DBG_FSM_STARTPOWDOWN 0xf |
| 116 | #define HC_DBG_FORCE_DATA_MODE 0x40000 |
| 117 | |
| 118 | /* Settings */ |
| 119 | #define HC_FIFO_SIZE 16 |
| 120 | #define HC_FIFO_THRESH_READ 4 |
| 121 | #define HC_FIFO_THRESH_WRITE 4 |
| 122 | |
| 123 | #define HC_TIMEOUT_DEFAULT 0x00f00000 |
| 124 | #define HC_TIMEOUT_IDLE 0x00a00000 |
| 125 | |
| 126 | #endif /* RPI3_SDHOST_H */ |