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Dan Handleye2c27f52014-08-01 17:58:27 +01001/*
Alexei Fedorov7d616ee2020-11-13 12:36:49 +00002 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
Dan Handleye2c27f52014-08-01 17:58:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handleye2c27f52014-08-01 17:58:27 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef TSP_PRIVATE_H
8#define TSP_PRIVATE_H
Dan Handleye2c27f52014-08-01 17:58:27 +01009
10/* Definitions to help the assembler access the SMC/ERET args structure */
11#define TSP_ARGS_SIZE 0x40
12#define TSP_ARG0 0x0
13#define TSP_ARG1 0x8
14#define TSP_ARG2 0x10
15#define TSP_ARG3 0x18
16#define TSP_ARG4 0x20
17#define TSP_ARG5 0x28
18#define TSP_ARG6 0x30
19#define TSP_ARG7 0x38
20#define TSP_ARGS_END 0x40
21
22
Julius Werner53456fc2019-07-09 13:49:11 -070023#ifndef __ASSEMBLER__
Dan Handleye2c27f52014-08-01 17:58:27 +010024
Dan Handleye2c27f52014-08-01 17:58:27 +010025#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000026
27#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */
Dan Handleye2c27f52014-08-01 17:58:27 +010028
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000029#include <bl32/tsp/tsp.h>
30#include <lib/cassert.h>
31#include <lib/spinlock.h>
Dan Handleye2c27f52014-08-01 17:58:27 +010032
33typedef struct work_statistics {
Soby Mathewbec98512015-09-03 18:29:38 +010034 /* Number of s-el1 interrupts on this cpu */
35 uint32_t sel1_intr_count;
Soby Mathewbc912822015-09-22 12:01:18 +010036 /* Number of non s-el1 interrupts on this cpu which preempted TSP */
37 uint32_t preempt_intr_count;
Soby Mathewbec98512015-09-03 18:29:38 +010038 /* Number of sync s-el1 interrupts on this cpu */
39 uint32_t sync_sel1_intr_count;
40 /* Number of s-el1 interrupts returns on this cpu */
41 uint32_t sync_sel1_intr_ret_count;
Dan Handleye2c27f52014-08-01 17:58:27 +010042 uint32_t smc_count; /* Number of returns on this cpu */
43 uint32_t eret_count; /* Number of entries on this cpu */
44 uint32_t cpu_on_count; /* Number of cpu on requests */
45 uint32_t cpu_off_count; /* Number of cpu off requests */
46 uint32_t cpu_suspend_count; /* Number of cpu suspend requests */
47 uint32_t cpu_resume_count; /* Number of cpu resume requests */
48} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t;
49
50typedef struct tsp_args {
51 uint64_t _regs[TSP_ARGS_END >> 3];
52} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t;
53
54/* Macros to access members of the above structure using their offsets */
55#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3])
56#define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \
57 = val)
58/*
59 * Ensure that the assembler's view of the size of the tsp_args is the
60 * same as the compilers
61 */
62CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch);
63
Alexei Fedorov7d616ee2020-11-13 12:36:49 +000064uint128_t tsp_get_magic(void);
Dan Handleye2c27f52014-08-01 17:58:27 +010065
Roberto Vargas69abcd42018-02-12 12:36:17 +000066tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
Dan Handleye2c27f52014-08-01 17:58:27 +010067 uint64_t arg1,
68 uint64_t arg2,
69 uint64_t arg3,
70 uint64_t arg4,
71 uint64_t arg5,
72 uint64_t arg6,
73 uint64_t arg7);
74tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
75 uint64_t arg1,
76 uint64_t arg2,
77 uint64_t arg3,
78 uint64_t arg4,
79 uint64_t arg5,
80 uint64_t arg6,
81 uint64_t arg7);
82tsp_args_t *tsp_cpu_on_main(void);
83tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
84 uint64_t arg1,
85 uint64_t arg2,
86 uint64_t arg3,
87 uint64_t arg4,
88 uint64_t arg5,
89 uint64_t arg6,
90 uint64_t arg7);
91
92/* Generic Timer functions */
93void tsp_generic_timer_start(void);
94void tsp_generic_timer_handler(void);
95void tsp_generic_timer_stop(void);
96void tsp_generic_timer_save(void);
97void tsp_generic_timer_restore(void);
98
Soby Mathewbec98512015-09-03 18:29:38 +010099/* S-EL1 interrupt management functions */
100void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
Dan Handleye2c27f52014-08-01 17:58:27 +0100101
102
103/* Data structure to keep track of TSP statistics */
104extern spinlock_t console_lock;
105extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
106
107/* Vector table of jumps */
108extern tsp_vectors_t tsp_vector_table;
109
Roberto Vargasd4b35e12018-02-12 12:36:17 +0000110/* functions */
111int32_t tsp_common_int_handler(void);
112int32_t tsp_handle_preemption(void);
113
114tsp_args_t *tsp_abort_smc_handler(uint64_t func,
115 uint64_t arg1,
116 uint64_t arg2,
117 uint64_t arg3,
118 uint64_t arg4,
119 uint64_t arg5,
120 uint64_t arg6,
121 uint64_t arg7);
122
123tsp_args_t *tsp_smc_handler(uint64_t func,
124 uint64_t arg1,
125 uint64_t arg2,
126 uint64_t arg3,
127 uint64_t arg4,
128 uint64_t arg5,
129 uint64_t arg6,
130 uint64_t arg7);
131
132tsp_args_t *tsp_system_reset_main(uint64_t arg0,
133 uint64_t arg1,
134 uint64_t arg2,
135 uint64_t arg3,
136 uint64_t arg4,
137 uint64_t arg5,
138 uint64_t arg6,
139 uint64_t arg7);
140
141tsp_args_t *tsp_system_off_main(uint64_t arg0,
142 uint64_t arg1,
143 uint64_t arg2,
144 uint64_t arg3,
145 uint64_t arg4,
146 uint64_t arg5,
147 uint64_t arg6,
148 uint64_t arg7);
Dan Handleye2c27f52014-08-01 17:58:27 +0100149
Roberto Vargasd4b35e12018-02-12 12:36:17 +0000150uint64_t tsp_main(void);
Julius Werner53456fc2019-07-09 13:49:11 -0700151#endif /* __ASSEMBLER__ */
Dan Handleye2c27f52014-08-01 17:58:27 +0100152
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000153#endif /* TSP_PRIVATE_H */