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Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +02001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8/* Marvell CP110 ana A3700 common */
9
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000010#ifndef PHY_COMPHY_COMMON_H
11#define PHY_COMPHY_COMMON_H
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +020012
13/* #define DEBUG_COMPHY */
14#ifdef DEBUG_COMPHY
15#define debug(format...) printf(format)
16#else
17#define debug(format, arg...)
18#endif
19
20/* A lane is described by 4 fields:
21 * - bit 1~0 represent comphy polarity invert
22 * - bit 7~2 represent comphy speed
23 * - bit 11~8 represent unit index
24 * - bit 16~12 represent mode
25 * - bit 17 represent comphy indication of clock source
26 * - bit 19-18 represents pcie width (in case of pcie comphy config.)
27 * - bit 31~20 reserved
28 */
29
30#define COMPHY_INVERT_OFFSET 0
31#define COMPHY_INVERT_LEN 2
32#define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, \
33 COMPHY_INVERT_LEN)
34#define COMPHY_SPEED_OFFSET (COMPHY_INVERT_OFFSET + COMPHY_INVERT_LEN)
35#define COMPHY_SPEED_LEN 6
36#define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, \
37 COMPHY_SPEED_LEN)
38#define COMPHY_UNIT_ID_OFFSET (COMPHY_SPEED_OFFSET + COMPHY_SPEED_LEN)
39#define COMPHY_UNIT_ID_LEN 4
40#define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, \
41 COMPHY_UNIT_ID_LEN)
42#define COMPHY_MODE_OFFSET (COMPHY_UNIT_ID_OFFSET + COMPHY_UNIT_ID_LEN)
43#define COMPHY_MODE_LEN 5
44#define COMPHY_MODE_MASK COMPHY_MASK(COMPHY_MODE_OFFSET, COMPHY_MODE_LEN)
45#define COMPHY_CLK_SRC_OFFSET (COMPHY_MODE_OFFSET + COMPHY_MODE_LEN)
46#define COMPHY_CLK_SRC_LEN 1
47#define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, \
48 COMPHY_CLK_SRC_LEN)
49#define COMPHY_PCI_WIDTH_OFFSET (COMPHY_CLK_SRC_OFFSET + COMPHY_CLK_SRC_LEN)
50#define COMPHY_PCI_WIDTH_LEN 3
51#define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, \
52 COMPHY_PCI_WIDTH_LEN)
53
54#define COMPHY_MASK(offset, len) (((1 << (len)) - 1) << (offset))
55
56/* Macro which extracts mode from lane description */
57#define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> \
58 COMPHY_MODE_OFFSET)
59/* Macro which extracts unit index from lane description */
60#define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> \
61 COMPHY_UNIT_ID_OFFSET)
62/* Macro which extracts speed from lane description */
63#define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> \
64 COMPHY_SPEED_OFFSET)
65/* Macro which extracts clock source indication from lane description */
66#define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> \
67 COMPHY_CLK_SRC_OFFSET)
68/* Macro which extracts pcie width indication from lane description */
69#define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> \
70 COMPHY_PCI_WIDTH_OFFSET)
71
72/* Macro which extracts the polarity invert from lane description */
73#define COMPHY_GET_POLARITY_INVERT(x) (((x) & COMPHY_INVERT_MASK) >> \
74 COMPHY_INVERT_OFFSET)
75
76
77#define COMPHY_SATA_MODE 0x1
78#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
79#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
80#define COMPHY_USB3H_MODE 0x4
81#define COMPHY_USB3D_MODE 0x5
82#define COMPHY_PCIE_MODE 0x6
83#define COMPHY_RXAUI_MODE 0x7
84#define COMPHY_XFI_MODE 0x8
85#define COMPHY_SFI_MODE 0x9
86#define COMPHY_USB3_MODE 0xa
87#define COMPHY_AP_MODE 0xb
88
89#define COMPHY_UNUSED 0xFFFFFFFF
90
91/* Polarity invert macro */
92#define COMPHY_POLARITY_NO_INVERT 0
93#define COMPHY_POLARITY_TXD_INVERT 1
94#define COMPHY_POLARITY_RXD_INVERT 2
95#define COMPHY_POLARITY_ALL_INVERT (COMPHY_POLARITY_TXD_INVERT | \
96 COMPHY_POLARITY_RXD_INVERT)
97
98enum reg_width_type {
99 REG_16BIT = 0,
100 REG_32BIT,
101};
102
103enum {
104 COMPHY_LANE0 = 0,
105 COMPHY_LANE1,
106 COMPHY_LANE2,
107 COMPHY_LANE3,
108 COMPHY_LANE4,
109 COMPHY_LANE5,
110 COMPHY_LANE_MAX,
111};
112
113static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val,
114 uint32_t mask,
115 uint32_t usec_timeout,
116 enum reg_width_type type)
117{
118 uint32_t data;
119
120 do {
121 udelay(1);
122 if (type == REG_16BIT)
123 data = mmio_read_16(addr) & mask;
124 else
125 data = mmio_read_32(addr) & mask;
126 } while (data != val && --usec_timeout > 0);
127
128 if (usec_timeout == 0)
129 return data;
130
131 return 0;
132}
133
134static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask)
135{
136 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
137 addr, data, mask);
138 debug("old value = 0x%x ==> ", mmio_read_32(addr));
139 mmio_clrsetbits_32(addr, mask, data);
140
141 debug("new val 0x%x\n", mmio_read_32(addr));
142}
143
144static inline void __unused reg_set16(uintptr_t addr, uint16_t data,
145 uint16_t mask)
146{
147
148 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
149 addr, data, mask);
150 debug("old value = 0x%x ==> ", mmio_read_16(addr));
151 mmio_clrsetbits_16(addr, mask, data);
152
153 debug("new val 0x%x\n", mmio_read_16(addr));
154}
155
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000156#endif /* PHY_COMPHY_COMMON_H */