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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Antonio Nino Diazc326c342019-01-11 11:20:10 +00002 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef ARCH_H
8#define ARCH_H
Soby Mathewc6820d12016-05-09 17:49:55 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Isla Mitchell02c63072017-07-21 14:44:36 +010011
Soby Mathewc6820d12016-05-09 17:49:55 +010012/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(24)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_REV_SHIFT U(0)
20#define MIDR_REV_BITS U(4)
21#define MIDR_PN_MASK U(0xfff)
22#define MIDR_PN_SHIFT U(4)
Soby Mathewc6820d12016-05-09 17:49:55 +010023
24/*******************************************************************************
25 * MPIDR macros
26 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010027#define MPIDR_MT_MASK (U(1) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +010028#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
29#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_AFFINITY_BITS U(8)
31#define MPIDR_AFFLVL_MASK U(0xff)
32#define MPIDR_AFFLVL_SHIFT U(3)
33#define MPIDR_AFF0_SHIFT U(0)
34#define MPIDR_AFF1_SHIFT U(8)
35#define MPIDR_AFF2_SHIFT U(16)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000036#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010037#define MPIDR_AFFINITY_MASK U(0x00ffffff)
38#define MPIDR_AFFLVL0 U(0)
39#define MPIDR_AFFLVL1 U(1)
40#define MPIDR_AFFLVL2 U(2)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000041#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Soby Mathewc6820d12016-05-09 17:49:55 +010042
43#define MPIDR_AFFLVL0_VAL(mpidr) \
44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
45#define MPIDR_AFFLVL1_VAL(mpidr) \
46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
47#define MPIDR_AFFLVL2_VAL(mpidr) \
48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010049#define MPIDR_AFFLVL3_VAL(mpidr) U(0)
Soby Mathewc6820d12016-05-09 17:49:55 +010050
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000051#define MPIDR_AFF_ID(mpid, n) \
52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
53
54#define MPID_MASK (MPIDR_MT_MASK |\
55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
58
59/*
60 * An invalid MPID. This value can be used by functions that return an MPID to
61 * indicate an error.
62 */
63#define INVALID_MPID U(0xFFFFFFFF)
64
Soby Mathewc6820d12016-05-09 17:49:55 +010065/*
66 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
67 * add one while using this macro to define array sizes.
68 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010069#define MPIDR_MAX_AFFLVL U(2)
Soby Mathewc6820d12016-05-09 17:49:55 +010070
71/* Data Cache set/way op type defines */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010072#define DC_OP_ISW U(0x0)
73#define DC_OP_CISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000074#if ERRATA_A53_827319
75#define DC_OP_CSW DC_OP_CISW
76#else
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010077#define DC_OP_CSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000078#endif
Soby Mathewc6820d12016-05-09 17:49:55 +010079
80/*******************************************************************************
81 * Generic timer memory mapped registers & offsets
82 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010083#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +020084/* Counter Count Value Lower register */
85#define CNTCVL_OFF U(0x008)
86/* Counter Count Value Upper register */
87#define CNTCVU_OFF U(0x00C)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010088#define CNTFID_OFF U(0x020)
Soby Mathewc6820d12016-05-09 17:49:55 +010089
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010090#define CNTCR_EN (U(1) << 0)
91#define CNTCR_HDBG (U(1) << 1)
Soby Mathewc6820d12016-05-09 17:49:55 +010092#define CNTCR_FCREQ(x) ((x) << 8)
93
94/*******************************************************************************
95 * System register bit definitions
96 ******************************************************************************/
97/* CLIDR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010098#define LOUIS_SHIFT U(21)
99#define LOC_SHIFT U(24)
100#define CLIDR_FIELD_WIDTH U(3)
Soby Mathewc6820d12016-05-09 17:49:55 +0100101
102/* CSSELR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100103#define LEVEL_SHIFT U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100104
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000105/* ID_MMFR4 definitions */
106#define ID_MMFR4_CNP_SHIFT U(12)
107#define ID_MMFR4_CNP_LENGTH U(4)
108#define ID_MMFR4_CNP_MASK U(0xf)
109
110/* ID_PFR0 definitions */
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100111#define ID_PFR0_AMU_SHIFT U(20)
112#define ID_PFR0_AMU_LENGTH U(4)
113#define ID_PFR0_AMU_MASK U(0xf)
114
Sathees Balya0911df12018-12-06 13:33:24 +0000115#define ID_PFR0_DIT_SHIFT U(24)
116#define ID_PFR0_DIT_LENGTH U(4)
117#define ID_PFR0_DIT_MASK U(0xf)
118#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
119
Soby Mathewc6820d12016-05-09 17:49:55 +0100120/* ID_PFR1 definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100121#define ID_PFR1_VIRTEXT_SHIFT U(12)
122#define ID_PFR1_VIRTEXT_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100123#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
124 & ID_PFR1_VIRTEXT_MASK)
Antonio Nino Diazd29d21e2019-02-06 09:23:04 +0000125#define ID_PFR1_GENTIMER_SHIFT U(16)
126#define ID_PFR1_GENTIMER_MASK U(0xf)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100127#define ID_PFR1_GIC_SHIFT U(28)
128#define ID_PFR1_GIC_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100129
130/* SCTLR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100131#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
132 (U(1) << 3))
Etienne Carriere70a004b2017-11-05 22:56:03 +0100133#if ARM_ARCH_MAJOR == 7
134#define SCTLR_RES1 SCTLR_RES1_DEF
135#else
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100136#define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
Etienne Carriere70a004b2017-11-05 22:56:03 +0100137#endif
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100138#define SCTLR_M_BIT (U(1) << 0)
139#define SCTLR_A_BIT (U(1) << 1)
140#define SCTLR_C_BIT (U(1) << 2)
141#define SCTLR_CP15BEN_BIT (U(1) << 5)
142#define SCTLR_ITD_BIT (U(1) << 7)
143#define SCTLR_Z_BIT (U(1) << 11)
144#define SCTLR_I_BIT (U(1) << 12)
145#define SCTLR_V_BIT (U(1) << 13)
146#define SCTLR_RR_BIT (U(1) << 14)
147#define SCTLR_NTWI_BIT (U(1) << 16)
148#define SCTLR_NTWE_BIT (U(1) << 18)
149#define SCTLR_WXN_BIT (U(1) << 19)
150#define SCTLR_UWXN_BIT (U(1) << 20)
151#define SCTLR_EE_BIT (U(1) << 25)
152#define SCTLR_TRE_BIT (U(1) << 28)
153#define SCTLR_AFE_BIT (U(1) << 29)
154#define SCTLR_TE_BIT (U(1) << 30)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000155#define SCTLR_DSSBS_BIT (U(1) << 31)
David Cunadofee86532017-04-13 22:38:29 +0100156#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
157 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
Soby Mathewc6820d12016-05-09 17:49:55 +0100158
dp-arm595d0d52017-02-08 11:51:50 +0000159/* SDCR definitions */
160#define SDCR_SPD(x) ((x) << 14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100161#define SDCR_SPD_LEGACY U(0x0)
162#define SDCR_SPD_DISABLE U(0x2)
163#define SDCR_SPD_ENABLE U(0x3)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000164#define SDCR_SCCD_BIT (U(1) << 23)
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100165#define SDCR_SPME_BIT (U(1) << 17)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100166#define SDCR_RESET_VAL U(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000167
Soby Mathewc6820d12016-05-09 17:49:55 +0100168/* HSCTLR definitions */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000169#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100170 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
171 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
172
173#define HSCTLR_M_BIT (U(1) << 0)
174#define HSCTLR_A_BIT (U(1) << 1)
175#define HSCTLR_C_BIT (U(1) << 2)
176#define HSCTLR_CP15BEN_BIT (U(1) << 5)
177#define HSCTLR_ITD_BIT (U(1) << 7)
178#define HSCTLR_SED_BIT (U(1) << 8)
179#define HSCTLR_I_BIT (U(1) << 12)
180#define HSCTLR_WXN_BIT (U(1) << 19)
181#define HSCTLR_EE_BIT (U(1) << 25)
182#define HSCTLR_TE_BIT (U(1) << 30)
Soby Mathewc6820d12016-05-09 17:49:55 +0100183
184/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100185#define CPACR_FPEN(x) ((x) << 20)
186#define CPACR_FP_TRAP_PL0 U(0x1)
187#define CPACR_FP_TRAP_ALL U(0x2)
188#define CPACR_FP_TRAP_NONE U(0x3)
Soby Mathewc6820d12016-05-09 17:49:55 +0100189
190/* SCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100191#define SCR_TWE_BIT (U(1) << 13)
192#define SCR_TWI_BIT (U(1) << 12)
193#define SCR_SIF_BIT (U(1) << 9)
194#define SCR_HCE_BIT (U(1) << 8)
195#define SCR_SCD_BIT (U(1) << 7)
196#define SCR_NET_BIT (U(1) << 6)
197#define SCR_AW_BIT (U(1) << 5)
198#define SCR_FW_BIT (U(1) << 4)
199#define SCR_EA_BIT (U(1) << 3)
200#define SCR_FIQ_BIT (U(1) << 2)
201#define SCR_IRQ_BIT (U(1) << 1)
202#define SCR_NS_BIT (U(1) << 0)
203#define SCR_VALID_BIT_MASK U(0x33ff)
204#define SCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100205
206#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
207
208/* HCR definitions */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000209#define HCR_TGE_BIT (U(1) << 27)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100210#define HCR_AMO_BIT (U(1) << 5)
211#define HCR_IMO_BIT (U(1) << 4)
212#define HCR_FMO_BIT (U(1) << 3)
213#define HCR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100214
215/* CNTHCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100216#define CNTHCTL_RESET_VAL U(0x0)
217#define PL1PCEN_BIT (U(1) << 1)
218#define PL1PCTEN_BIT (U(1) << 0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100219
220/* CNTKCTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100221#define PL0PTEN_BIT (U(1) << 9)
222#define PL0VTEN_BIT (U(1) << 8)
223#define PL0PCTEN_BIT (U(1) << 0)
224#define PL0VCTEN_BIT (U(1) << 1)
225#define EVNTEN_BIT (U(1) << 2)
226#define EVNTDIR_BIT (U(1) << 3)
227#define EVNTI_SHIFT U(4)
228#define EVNTI_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100229
230/* HCPTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100231#define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
232#define TCPAC_BIT (U(1) << 31)
233#define TAM_BIT (U(1) << 30)
234#define TTA_BIT (U(1) << 20)
Sandrine Bailleux6061c452018-07-13 10:04:12 +0200235#define TCP11_BIT (U(1) << 11)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100236#define TCP10_BIT (U(1) << 10)
David Cunadofee86532017-04-13 22:38:29 +0100237#define HCPTR_RESET_VAL HCPTR_RES1
238
239/* VTTBR defintions */
240#define VTTBR_RESET_VAL ULL(0x0)
241#define VTTBR_VMID_MASK ULL(0xff)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100242#define VTTBR_VMID_SHIFT U(48)
243#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
244#define VTTBR_BADDR_SHIFT U(0)
David Cunadofee86532017-04-13 22:38:29 +0100245
246/* HDCR definitions */
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100247#define HDCR_HLP_BIT (U(1) << 26)
248#define HDCR_HPME_BIT (U(1) << 7)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100249#define HDCR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100250
251/* HSTR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100252#define HSTR_RESET_VAL U(0x0)
David Cunadofee86532017-04-13 22:38:29 +0100253
254/* CNTHP_CTL definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100255#define CNTHP_CTL_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100256
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000257/* NSACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100258#define NSASEDIS_BIT (U(1) << 15)
259#define NSTRCDIS_BIT (U(1) << 20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100260#define NSACR_CP11_BIT (U(1) << 11)
261#define NSACR_CP10_BIT (U(1) << 10)
262#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
David Cunadofee86532017-04-13 22:38:29 +0100263#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100264#define NSACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100265
266/* CPACR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100267#define ASEDIS_BIT (U(1) << 31)
268#define TRCDIS_BIT (U(1) << 28)
269#define CPACR_CP11_SHIFT U(22)
270#define CPACR_CP10_SHIFT U(20)
271#define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
272 (U(0x3) << CPACR_CP10_SHIFT))
273#define CPACR_RESET_VAL U(0x0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100274
275/* FPEXC definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100276#define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
277#define FPEXC_EN_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100278#define FPEXC_RESET_VAL FPEXC_RES1
Soby Mathewc6820d12016-05-09 17:49:55 +0100279
280/* SPSR/CPSR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100281#define SPSR_FIQ_BIT (U(1) << 0)
282#define SPSR_IRQ_BIT (U(1) << 1)
283#define SPSR_ABT_BIT (U(1) << 2)
284#define SPSR_AIF_SHIFT U(6)
285#define SPSR_AIF_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100286
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100287#define SPSR_E_SHIFT U(9)
288#define SPSR_E_MASK U(0x1)
289#define SPSR_E_LITTLE U(0)
290#define SPSR_E_BIG U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100291
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100292#define SPSR_T_SHIFT U(5)
293#define SPSR_T_MASK U(0x1)
294#define SPSR_T_ARM U(0)
295#define SPSR_T_THUMB U(1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100296
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100297#define SPSR_MODE_SHIFT U(0)
298#define SPSR_MODE_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100299
John Tsichritzis55534172019-07-23 11:12:41 +0100300#define SPSR_SSBS_BIT BIT_32(23)
301
Soby Mathewc6820d12016-05-09 17:49:55 +0100302#define DISABLE_ALL_EXCEPTIONS \
303 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
304
Sathees Balya0911df12018-12-06 13:33:24 +0000305#define CPSR_DIT_BIT (U(1) << 21)
Soby Mathewc6820d12016-05-09 17:49:55 +0100306/*
307 * TTBCR definitions
308 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100309#define TTBCR_EAE_BIT (U(1) << 31)
Soby Mathewc6820d12016-05-09 17:49:55 +0100310
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100311#define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
312#define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
313#define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
Soby Mathewc6820d12016-05-09 17:49:55 +0100314
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100315#define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
316#define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
317#define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
318#define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
Soby Mathewc6820d12016-05-09 17:49:55 +0100319
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100320#define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
321#define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
322#define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
323#define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
Soby Mathewc6820d12016-05-09 17:49:55 +0100324
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100325#define TTBCR_EPD1_BIT (U(1) << 23)
326#define TTBCR_A1_BIT (U(1) << 22)
Soby Mathewc6820d12016-05-09 17:49:55 +0100327
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100328#define TTBCR_T1SZ_SHIFT U(16)
329#define TTBCR_T1SZ_MASK U(0x7)
330#define TTBCR_TxSZ_MIN U(0)
331#define TTBCR_TxSZ_MAX U(7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100332
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100333#define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
334#define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
335#define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
Soby Mathewc6820d12016-05-09 17:49:55 +0100336
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100337#define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
338#define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
339#define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
340#define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
Soby Mathewc6820d12016-05-09 17:49:55 +0100341
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100342#define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
343#define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
344#define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
345#define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
Soby Mathewc6820d12016-05-09 17:49:55 +0100346
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100347#define TTBCR_EPD0_BIT (U(1) << 7)
348#define TTBCR_T0SZ_SHIFT U(0)
349#define TTBCR_T0SZ_MASK U(0x7)
Soby Mathewc6820d12016-05-09 17:49:55 +0100350
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100351/*
352 * HTCR definitions
353 */
354#define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
355
356#define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
357#define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
358#define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
359
360#define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
361#define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
362#define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
363#define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
364
365#define HTCR_RGN0_INNER_NC (U(0x0) << 8)
366#define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
367#define HTCR_RGN0_INNER_WT (U(0x2) << 8)
368#define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
369
370#define HTCR_T0SZ_SHIFT U(0)
371#define HTCR_T0SZ_MASK U(0x7)
372
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100373#define MODE_RW_SHIFT U(0x4)
374#define MODE_RW_MASK U(0x1)
375#define MODE_RW_32 U(0x1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100376
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100377#define MODE32_SHIFT U(0)
378#define MODE32_MASK U(0x1f)
379#define MODE32_usr U(0x10)
380#define MODE32_fiq U(0x11)
381#define MODE32_irq U(0x12)
382#define MODE32_svc U(0x13)
383#define MODE32_mon U(0x16)
384#define MODE32_abt U(0x17)
385#define MODE32_hyp U(0x1a)
386#define MODE32_und U(0x1b)
387#define MODE32_sys U(0x1f)
Soby Mathewc6820d12016-05-09 17:49:55 +0100388
389#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
390
391#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100392 ((MODE_RW_32 << MODE_RW_SHIFT | \
Soby Mathewc6820d12016-05-09 17:49:55 +0100393 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
394 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
395 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
John Tsichritzis55534172019-07-23 11:12:41 +0100396 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \
397 (~(SPSR_SSBS_BIT)))
Soby Mathewc6820d12016-05-09 17:49:55 +0100398
399/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100400 * TTBR definitions
401 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100402#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100403
404/*
Soby Mathewc6820d12016-05-09 17:49:55 +0100405 * CTR definitions
406 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100407#define CTR_CWG_SHIFT U(24)
408#define CTR_CWG_MASK U(0xf)
409#define CTR_ERG_SHIFT U(20)
410#define CTR_ERG_MASK U(0xf)
411#define CTR_DMINLINE_SHIFT U(16)
412#define CTR_DMINLINE_WIDTH U(4)
413#define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
414#define CTR_L1IP_SHIFT U(14)
415#define CTR_L1IP_MASK U(0x3)
416#define CTR_IMINLINE_SHIFT U(0)
417#define CTR_IMINLINE_MASK U(0xf)
Soby Mathewc6820d12016-05-09 17:49:55 +0100418
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100419#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Soby Mathewc6820d12016-05-09 17:49:55 +0100420
David Cunado5f55e282016-10-31 17:37:34 +0000421/* PMCR definitions */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100422#define PMCR_N_SHIFT U(11)
423#define PMCR_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000424#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100425#define PMCR_LP_BIT (U(1) << 7)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100426#define PMCR_LC_BIT (U(1) << 6)
427#define PMCR_DP_BIT (U(1) << 5)
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100428#define PMCR_RESET_VAL U(0x0)
David Cunado5f55e282016-10-31 17:37:34 +0000429
Soby Mathewc6820d12016-05-09 17:49:55 +0100430/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000431 * Definitions of register offsets, fields and macros for CPU system
432 * instructions.
433 ******************************************************************************/
434
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100435#define TLBI_ADDR_SHIFT U(0)
436#define TLBI_ADDR_MASK U(0xFFFFF000)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000437#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
438
439/*******************************************************************************
Soby Mathewc6820d12016-05-09 17:49:55 +0100440 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
441 * system level implementation of the Generic Timer.
442 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100443#define CNTCTLBASE_CNTFRQ U(0x0)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100444#define CNTNSAR U(0x4)
Soby Mathewc6820d12016-05-09 17:49:55 +0100445#define CNTNSAR_NS_SHIFT(x) (x)
446
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100447#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
448#define CNTACR_RPCT_SHIFT U(0x0)
449#define CNTACR_RVCT_SHIFT U(0x1)
450#define CNTACR_RFRQ_SHIFT U(0x2)
451#define CNTACR_RVOFF_SHIFT U(0x3)
452#define CNTACR_RWVT_SHIFT U(0x4)
453#define CNTACR_RWPT_SHIFT U(0x5)
Soby Mathewc6820d12016-05-09 17:49:55 +0100454
Soby Mathew2d9f7952018-06-11 16:21:30 +0100455/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000456 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100457 * system level implementation of the Generic Timer.
458 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000459/* Physical Count register. */
460#define CNTPCT_LO U(0x0)
461/* Counter Frequency register. */
462#define CNTBASEN_CNTFRQ U(0x10)
463/* Physical Timer CompareValue register. */
464#define CNTP_CVAL_LO U(0x20)
465/* Physical Timer Control register. */
466#define CNTP_CTL U(0x2c)
467
468/* Physical timer control register bit fields shifts and masks */
469#define CNTP_CTL_ENABLE_SHIFT 0
470#define CNTP_CTL_IMASK_SHIFT 1
471#define CNTP_CTL_ISTATUS_SHIFT 2
472
473#define CNTP_CTL_ENABLE_MASK U(1)
474#define CNTP_CTL_IMASK_MASK U(1)
475#define CNTP_CTL_ISTATUS_MASK U(1)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100476
Soby Mathewc6820d12016-05-09 17:49:55 +0100477/* MAIR macros */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000478#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
479#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
Soby Mathewc6820d12016-05-09 17:49:55 +0100480
481/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
482#define SCR p15, 0, c1, c1, 0
483#define SCTLR p15, 0, c1, c0, 0
Etienne Carriere70a004b2017-11-05 22:56:03 +0100484#define ACTLR p15, 0, c1, c0, 1
dp-arm595d0d52017-02-08 11:51:50 +0000485#define SDCR p15, 0, c1, c3, 1
Soby Mathewc6820d12016-05-09 17:49:55 +0100486#define MPIDR p15, 0, c0, c0, 5
487#define MIDR p15, 0, c0, c0, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000488#define HVBAR p15, 4, c12, c0, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100489#define VBAR p15, 0, c12, c0, 0
490#define MVBAR p15, 0, c12, c0, 1
491#define NSACR p15, 0, c1, c1, 2
492#define CPACR p15, 0, c1, c0, 2
493#define DCCIMVAC p15, 0, c7, c14, 1
494#define DCCMVAC p15, 0, c7, c10, 1
495#define DCIMVAC p15, 0, c7, c6, 1
496#define DCCISW p15, 0, c7, c14, 2
497#define DCCSW p15, 0, c7, c10, 2
498#define DCISW p15, 0, c7, c6, 2
499#define CTR p15, 0, c0, c0, 1
500#define CNTFRQ p15, 0, c14, c0, 0
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000501#define ID_MMFR4 p15, 0, c0, c2, 6
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100502#define ID_PFR0 p15, 0, c0, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100503#define ID_PFR1 p15, 0, c0, c1, 1
504#define MAIR0 p15, 0, c10, c2, 0
505#define MAIR1 p15, 0, c10, c2, 1
506#define TTBCR p15, 0, c2, c0, 2
507#define TTBR0 p15, 0, c2, c0, 0
508#define TTBR1 p15, 0, c2, c0, 1
509#define TLBIALL p15, 0, c8, c7, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000510#define TLBIALLH p15, 4, c8, c7, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100511#define TLBIALLIS p15, 0, c8, c3, 0
512#define TLBIMVA p15, 0, c8, c7, 1
513#define TLBIMVAA p15, 0, c8, c7, 3
Antonio Nino Diazac998032017-02-27 17:23:54 +0000514#define TLBIMVAAIS p15, 0, c8, c3, 3
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100515#define TLBIMVAHIS p15, 4, c8, c3, 1
Antonio Nino Diazac998032017-02-27 17:23:54 +0000516#define BPIALLIS p15, 0, c7, c1, 6
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000517#define BPIALL p15, 0, c7, c5, 6
518#define ICIALLU p15, 0, c7, c5, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100519#define HSCTLR p15, 4, c1, c0, 0
520#define HCR p15, 4, c1, c1, 0
521#define HCPTR p15, 4, c1, c1, 2
David Cunadofee86532017-04-13 22:38:29 +0100522#define HSTR p15, 4, c1, c1, 3
Soby Mathewc6820d12016-05-09 17:49:55 +0100523#define CNTHCTL p15, 4, c14, c1, 0
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000524#define CNTKCTL p15, 0, c14, c1, 0
Soby Mathewc6820d12016-05-09 17:49:55 +0100525#define VPIDR p15, 4, c0, c0, 0
526#define VMPIDR p15, 4, c0, c0, 5
527#define ISR p15, 0, c12, c1, 0
528#define CLIDR p15, 1, c0, c0, 1
529#define CSSELR p15, 2, c0, c0, 0
530#define CCSIDR p15, 1, c0, c0, 0
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100531#define HTCR p15, 4, c2, c0, 2
532#define HMAIR0 p15, 4, c10, c2, 0
Douglas Raillard77414632018-08-21 12:54:45 +0100533#define ATS1CPR p15, 0, c7, c8, 0
534#define ATS1HR p15, 4, c7, c8, 0
Yatharth Kochara9f776c2016-11-10 16:17:51 +0000535#define DBGOSDLR p14, 0, c1, c3, 4
Soby Mathewc6820d12016-05-09 17:49:55 +0100536
David Cunado5f55e282016-10-31 17:37:34 +0000537/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
538#define HDCR p15, 4, c1, c1, 1
David Cunado5f55e282016-10-31 17:37:34 +0000539#define PMCR p15, 0, c9, c12, 0
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000540#define CNTHP_TVAL p15, 4, c14, c2, 0
David Cunadoc14b08e2016-11-25 00:21:59 +0000541#define CNTHP_CTL p15, 4, c14, c2, 1
David Cunado5f55e282016-10-31 17:37:34 +0000542
Etienne Carriere70a004b2017-11-05 22:56:03 +0100543/* AArch32 coproc registers for 32bit MMU descriptor support */
544#define PRRR p15, 0, c10, c2, 0
545#define NMRR p15, 0, c10, c2, 1
546#define DACR p15, 0, c3, c0, 0
547
Soby Mathewc6820d12016-05-09 17:49:55 +0100548/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
549#define ICC_IAR1 p15, 0, c12, c12, 0
550#define ICC_IAR0 p15, 0, c12, c8, 0
551#define ICC_EOIR1 p15, 0, c12, c12, 1
552#define ICC_EOIR0 p15, 0, c12, c8, 1
553#define ICC_HPPIR1 p15, 0, c12, c12, 2
554#define ICC_HPPIR0 p15, 0, c12, c8, 2
555#define ICC_BPR1 p15, 0, c12, c12, 3
556#define ICC_BPR0 p15, 0, c12, c8, 3
557#define ICC_DIR p15, 0, c12, c11, 1
558#define ICC_PMR p15, 0, c4, c6, 0
559#define ICC_RPR p15, 0, c12, c11, 3
560#define ICC_CTLR p15, 0, c12, c12, 4
561#define ICC_MCTLR p15, 6, c12, c12, 4
562#define ICC_SRE p15, 0, c12, c12, 5
563#define ICC_HSRE p15, 4, c12, c9, 5
564#define ICC_MSRE p15, 6, c12, c12, 5
565#define ICC_IGRPEN0 p15, 0, c12, c12, 6
566#define ICC_IGRPEN1 p15, 0, c12, c12, 7
567#define ICC_MGRPEN1 p15, 6, c12, c12, 7
568
569/* 64 bit system register defines The format is: coproc, opt1, CRm */
570#define TTBR0_64 p15, 0, c2
571#define TTBR1_64 p15, 1, c2
572#define CNTVOFF_64 p15, 4, c14
573#define VTTBR_64 p15, 6, c2
574#define CNTPCT_64 p15, 0, c14
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100575#define HTTBR_64 p15, 4, c2
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000576#define CNTHP_CVAL_64 p15, 6, c14
Douglas Raillard77414632018-08-21 12:54:45 +0100577#define PAR_64 p15, 0, c7
Soby Mathewc6820d12016-05-09 17:49:55 +0100578
579/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
580#define ICC_SGI1R_EL1_64 p15, 0, c12
581#define ICC_ASGI1R_EL1_64 p15, 1, c12
582#define ICC_SGI0R_EL1_64 p15, 2, c12
583
Isla Mitchell02c63072017-07-21 14:44:36 +0100584/*******************************************************************************
585 * Definitions of MAIR encodings for device and normal memory
586 ******************************************************************************/
587/*
588 * MAIR encodings for device memory attributes.
589 */
590#define MAIR_DEV_nGnRnE U(0x0)
591#define MAIR_DEV_nGnRE U(0x4)
592#define MAIR_DEV_nGRE U(0x8)
593#define MAIR_DEV_GRE U(0xc)
594
595/*
596 * MAIR encodings for normal memory attributes.
597 *
598 * Cache Policy
599 * WT: Write Through
600 * WB: Write Back
601 * NC: Non-Cacheable
602 *
603 * Transient Hint
604 * NTR: Non-Transient
605 * TR: Transient
606 *
607 * Allocation Policy
608 * RA: Read Allocate
609 * WA: Write Allocate
610 * RWA: Read and Write Allocate
611 * NA: No Allocation
612 */
613#define MAIR_NORM_WT_TR_WA U(0x1)
614#define MAIR_NORM_WT_TR_RA U(0x2)
615#define MAIR_NORM_WT_TR_RWA U(0x3)
616#define MAIR_NORM_NC U(0x4)
617#define MAIR_NORM_WB_TR_WA U(0x5)
618#define MAIR_NORM_WB_TR_RA U(0x6)
619#define MAIR_NORM_WB_TR_RWA U(0x7)
620#define MAIR_NORM_WT_NTR_NA U(0x8)
621#define MAIR_NORM_WT_NTR_WA U(0x9)
622#define MAIR_NORM_WT_NTR_RA U(0xa)
623#define MAIR_NORM_WT_NTR_RWA U(0xb)
624#define MAIR_NORM_WB_NTR_NA U(0xc)
625#define MAIR_NORM_WB_NTR_WA U(0xd)
626#define MAIR_NORM_WB_NTR_RA U(0xe)
627#define MAIR_NORM_WB_NTR_RWA U(0xf)
628
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100629#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100630
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100631#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
632 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100633
Douglas Raillard77414632018-08-21 12:54:45 +0100634/* PAR fields */
635#define PAR_F_SHIFT U(0)
636#define PAR_F_MASK ULL(0x1)
637#define PAR_ADDR_SHIFT U(12)
Yann Gautier812c3252018-09-20 15:48:52 +0200638#define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
Douglas Raillard77414632018-08-21 12:54:45 +0100639
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100640/*******************************************************************************
641 * Definitions for system register interface to AMU for ARMv8.4 onwards
642 ******************************************************************************/
643#define AMCR p15, 0, c13, c2, 0
644#define AMCFGR p15, 0, c13, c2, 1
645#define AMCGCR p15, 0, c13, c2, 2
646#define AMUSERENR p15, 0, c13, c2, 3
647#define AMCNTENCLR0 p15, 0, c13, c2, 4
648#define AMCNTENSET0 p15, 0, c13, c2, 5
649#define AMCNTENCLR1 p15, 0, c13, c3, 0
Joel Hutton0dcdd8d2017-12-21 15:21:20 +0000650#define AMCNTENSET1 p15, 0, c13, c3, 1
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100651
652/* Activity Monitor Group 0 Event Counter Registers */
653#define AMEVCNTR00 p15, 0, c0
654#define AMEVCNTR01 p15, 1, c0
655#define AMEVCNTR02 p15, 2, c0
656#define AMEVCNTR03 p15, 3, c0
657
658/* Activity Monitor Group 0 Event Type Registers */
659#define AMEVTYPER00 p15, 0, c13, c6, 0
660#define AMEVTYPER01 p15, 0, c13, c6, 1
661#define AMEVTYPER02 p15, 0, c13, c6, 2
662#define AMEVTYPER03 p15, 0, c13, c6, 3
663
Joel Hutton2691bc62017-12-12 15:47:55 +0000664/* Activity Monitor Group 1 Event Counter Registers */
665#define AMEVCNTR10 p15, 0, c4
666#define AMEVCNTR11 p15, 1, c4
667#define AMEVCNTR12 p15, 2, c4
668#define AMEVCNTR13 p15, 3, c4
669#define AMEVCNTR14 p15, 4, c4
670#define AMEVCNTR15 p15, 5, c4
671#define AMEVCNTR16 p15, 6, c4
672#define AMEVCNTR17 p15, 7, c4
673#define AMEVCNTR18 p15, 0, c5
674#define AMEVCNTR19 p15, 1, c5
675#define AMEVCNTR1A p15, 2, c5
676#define AMEVCNTR1B p15, 3, c5
677#define AMEVCNTR1C p15, 4, c5
678#define AMEVCNTR1D p15, 5, c5
679#define AMEVCNTR1E p15, 6, c5
680#define AMEVCNTR1F p15, 7, c5
681
682/* Activity Monitor Group 1 Event Type Registers */
683#define AMEVTYPER10 p15, 0, c13, c14, 0
684#define AMEVTYPER11 p15, 0, c13, c14, 1
685#define AMEVTYPER12 p15, 0, c13, c14, 2
686#define AMEVTYPER13 p15, 0, c13, c14, 3
687#define AMEVTYPER14 p15, 0, c13, c14, 4
688#define AMEVTYPER15 p15, 0, c13, c14, 5
689#define AMEVTYPER16 p15, 0, c13, c14, 6
690#define AMEVTYPER17 p15, 0, c13, c14, 7
691#define AMEVTYPER18 p15, 0, c13, c15, 0
692#define AMEVTYPER19 p15, 0, c13, c15, 1
693#define AMEVTYPER1A p15, 0, c13, c15, 2
694#define AMEVTYPER1B p15, 0, c13, c15, 3
695#define AMEVTYPER1C p15, 0, c13, c15, 4
696#define AMEVTYPER1D p15, 0, c13, c15, 5
697#define AMEVTYPER1E p15, 0, c13, c15, 6
698#define AMEVTYPER1F p15, 0, c13, c15, 7
699
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000700#endif /* ARCH_H */