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Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
BenjaminLimJLa4a43272022-04-06 10:19:16 +08002 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <arch_helpers.h>
9#include <drivers/delay_timer.h>
10#include <lib/mmio.h>
BenjaminLimJLa4a43272022-04-06 10:19:16 +080011#include "socfpga_plat_def.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080012
Hadi Asyrafi6a240c72019-08-01 15:21:20 +080013#define SOCFPGA_GLOBAL_TIMER 0xffd01000
14#define SOCFPGA_GLOBAL_TIMER_EN 0x3
Hadi Asyrafi616da772019-06-27 11:34:03 +080015
BenjaminLimJLa4a43272022-04-06 10:19:16 +080016static timer_ops_t plat_timer_ops;
Hadi Asyrafi616da772019-06-27 11:34:03 +080017/********************************************************************
18 * The timer delay function
19 ********************************************************************/
20static uint32_t socfpga_get_timer_value(void)
21{
22 /*
23 * Generic delay timer implementation expects the timer to be a down
24 * counter. We apply bitwise NOT operator to the tick values returned
25 * by read_cntpct_el0() to simulate the down counter. The value is
26 * clipped from 64 to 32 bits.
27 */
28 return (uint32_t)(~read_cntpct_el0());
29}
30
BenjaminLimJLa4a43272022-04-06 10:19:16 +080031void socfpga_delay_timer_init_args(void)
32{
33 plat_timer_ops.get_timer_value = socfpga_get_timer_value;
34 plat_timer_ops.clk_mult = 1;
35 plat_timer_ops.clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ;
36
37 timer_init(&plat_timer_ops);
38
39 NOTICE("BL31: MPU clock frequency: %d MHz\n", plat_timer_ops.clk_div);
40}
Hadi Asyrafi616da772019-06-27 11:34:03 +080041
42void socfpga_delay_timer_init(void)
43{
BenjaminLimJLa4a43272022-04-06 10:19:16 +080044 socfpga_delay_timer_init_args();
Hadi Asyrafi6a240c72019-08-01 15:21:20 +080045 mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
Tien Hock Loh64d2b2f2020-05-11 01:12:03 -070046
47 asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
48 asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));
49
Hadi Asyrafi616da772019-06-27 11:34:03 +080050}