developer | 5f73516 | 2021-01-04 00:02:34 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stddef.h> |
| 8 | |
| 9 | #include <assert.h> |
| 10 | #include <common/debug.h> |
| 11 | #include <lib/mmio.h> |
| 12 | |
| 13 | #include <mt_spm.h> |
| 14 | #include <mt_spm_internal.h> |
| 15 | #include <mt_spm_pmic_wrap.h> |
| 16 | #include <mt_spm_reg.h> |
| 17 | #include <mt_spm_resource_req.h> |
| 18 | #include <platform_def.h> |
| 19 | #include <plat_pm.h> |
| 20 | |
| 21 | /************************************** |
| 22 | * Define and Declare |
| 23 | **************************************/ |
| 24 | #define ROOT_CORE_ADDR_OFFSET 0x20000000 |
| 25 | #define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff |
| 26 | #define SPM_INIT_DONE_US 20 |
| 27 | |
| 28 | static unsigned int mt_spm_bblpm_cnt; |
| 29 | |
| 30 | const char *wakeup_src_str[32] = { |
| 31 | [0] = "R12_PCM_TIMER", |
| 32 | [1] = "R12_RESERVED_DEBUG_B", |
| 33 | [2] = "R12_KP_IRQ_B", |
| 34 | [3] = "R12_APWDT_EVENT_B", |
| 35 | [4] = "R12_APXGPT1_EVENT_B", |
| 36 | [5] = "R12_CONN2AP_SPM_WAKEUP_B", |
| 37 | [6] = "R12_EINT_EVENT_B", |
| 38 | [7] = "R12_CONN_WDT_IRQ_B", |
| 39 | [8] = "R12_CCIF0_EVENT_B", |
| 40 | [9] = "R12_LOWBATTERY_IRQ_B", |
| 41 | [10] = "R12_SC_SSPM2SPM_WAKEUP_B", |
| 42 | [11] = "R12_SC_SCP2SPM_WAKEUP_B", |
| 43 | [12] = "R12_SC_ADSP2SPM_WAKEUP_B", |
| 44 | [13] = "R12_PCM_WDT_WAKEUP_B", |
| 45 | [14] = "R12_USB_CDSC_B", |
| 46 | [15] = "R12_USB_POWERDWN_B", |
| 47 | [16] = "R12_SYS_TIMER_EVENT_B", |
| 48 | [17] = "R12_EINT_EVENT_SECURE_B", |
| 49 | [18] = "R12_CCIF1_EVENT_B", |
| 50 | [19] = "R12_UART0_IRQ_B", |
| 51 | [20] = "R12_AFE_IRQ_MCU_B", |
| 52 | [21] = "R12_THERM_CTRL_EVENT_B", |
| 53 | [22] = "R12_SYS_CIRQ_IRQ_B", |
| 54 | [23] = "R12_MD2AP_PEER_EVENT_B", |
| 55 | [24] = "R12_CSYSPWREQ_B", |
| 56 | [25] = "R12_MD1_WDT_B", |
| 57 | [26] = "R12_AP2AP_PEER_WAKEUPEVENT_B", |
| 58 | [27] = "R12_SEJ_EVENT_B", |
| 59 | [28] = "R12_SPM_CPU_WAKEUPEVENT_B", |
| 60 | [29] = "R12_APUSYS", |
| 61 | [30] = "R12_PCIE_BRIDGE_IRQ", |
| 62 | [31] = "R12_PCIE_IRQ", |
| 63 | }; |
| 64 | |
| 65 | /************************************** |
| 66 | * Function and API |
| 67 | **************************************/ |
| 68 | |
| 69 | wake_reason_t __spm_output_wake_reason(int state_id, |
| 70 | const struct wake_status *wakesta) |
| 71 | { |
| 72 | uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U; |
| 73 | wake_reason_t wr = WR_UNKNOWN; |
| 74 | |
| 75 | if (wakesta == NULL) { |
| 76 | return WR_UNKNOWN; |
| 77 | } |
| 78 | |
| 79 | if (wakesta->abort != 0U) { |
| 80 | ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n", |
| 81 | wakesta->abort, wakesta->timer_out); |
| 82 | } else { |
| 83 | for (i = 0U; i < 32U; i++) { |
| 84 | if ((wakesta->r12 & (1U << i)) != 0U) { |
| 85 | INFO("wake up by %s, timer_out = %u\n", |
| 86 | wakeup_src_str[i], wakesta->timer_out); |
| 87 | wr = WR_WAKE_SRC; |
| 88 | break; |
| 89 | } |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", |
| 94 | wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag, |
| 95 | wakesta->debug_flag1); |
| 96 | INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n", |
| 97 | wakesta->raw_sta, wakesta->md32pcm_wakeup_sta, |
| 98 | wakesta->md32pcm_event_sta, wakesta->idle_sta, |
| 99 | wakesta->cg_check_sta); |
| 100 | INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n", |
| 101 | wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2, |
| 102 | wakesta->req_sta3, wakesta->req_sta4, wakesta->isr); |
| 103 | INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n", |
| 104 | wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2); |
| 105 | INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n", |
| 106 | wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta); |
| 107 | INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n", |
| 108 | wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1, |
| 109 | wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req); |
| 110 | INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n", |
| 111 | wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), |
| 112 | mmio_read_32(SYS_TIMER_VALUE_H)); |
| 113 | |
| 114 | if (wakesta->timer_out != 0U) { |
| 115 | bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); |
| 116 | spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out; |
| 117 | INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct); |
| 118 | } |
| 119 | |
| 120 | return wr; |
| 121 | } |
| 122 | |
| 123 | void __spm_set_cpu_status(unsigned int cpu) |
| 124 | { |
| 125 | uint32_t root_core_addr; |
| 126 | |
| 127 | if (cpu < 8U) { |
| 128 | mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu)); |
| 129 | root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4); |
| 130 | root_core_addr += ROOT_CORE_ADDR_OFFSET; |
| 131 | mmio_write_32(ROOT_CORE_ADDR, root_core_addr); |
| 132 | /* Notify MCUPM that preferred cpu wakeup */ |
| 133 | mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu); |
| 134 | } else { |
| 135 | ERROR("%s: error cpu number %d\n", __func__, cpu); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, |
| 140 | unsigned int resource_usage) |
| 141 | { |
| 142 | uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ? |
| 143 | 1 : pwrctrl->reg_spm_apsrc_req; |
| 144 | uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ? |
| 145 | 1 : pwrctrl->reg_spm_ddr_en_req; |
| 146 | uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ? |
| 147 | 1 : pwrctrl->reg_spm_vrf18_req; |
| 148 | uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ? |
| 149 | 1 : pwrctrl->reg_spm_infra_req; |
| 150 | uint8_t f26m_req = ((resource_usage & |
| 151 | (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ? |
| 152 | 1 : pwrctrl->reg_spm_f26m_req; |
| 153 | |
| 154 | mmio_write_32(SPM_SRC_REQ, |
| 155 | ((apsrc_req & 0x1) << 0) | |
| 156 | ((f26m_req & 0x1) << 1) | |
| 157 | ((infra_req & 0x1) << 3) | |
| 158 | ((vrf18_req & 0x1) << 4) | |
| 159 | ((ddr_en_req & 0x1) << 7) | |
| 160 | ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | |
| 161 | ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | |
| 162 | ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | |
| 163 | ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | |
| 164 | ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); |
| 165 | } |
| 166 | |
| 167 | void __spm_set_power_control(const struct pwr_ctrl *pwrctrl) |
| 168 | { |
| 169 | /* Auto-gen Start */ |
| 170 | |
| 171 | /* SPM_AP_STANDBY_CON */ |
| 172 | mmio_write_32(SPM_AP_STANDBY_CON, |
| 173 | ((pwrctrl->reg_wfi_op & 0x1) << 0) | |
| 174 | ((pwrctrl->reg_wfi_type & 0x1) << 1) | |
| 175 | ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | |
| 176 | ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | |
| 177 | ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | |
| 178 | ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | |
| 179 | ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | |
| 180 | ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); |
| 181 | |
| 182 | /* SPM_SRC6_MASK */ |
| 183 | mmio_write_32(SPM_SRC6_MASK, |
| 184 | ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) | |
| 185 | ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) | |
| 186 | ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) | |
| 187 | ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) | |
| 188 | ((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4)); |
| 189 | |
| 190 | /* SPM_SRC_REQ */ |
| 191 | mmio_write_32(SPM_SRC_REQ, |
| 192 | ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | |
| 193 | ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | |
| 194 | ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | |
| 195 | ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | |
| 196 | ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | |
| 197 | ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | |
| 198 | ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | |
| 199 | ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | |
| 200 | ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | |
| 201 | ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); |
| 202 | |
| 203 | /* SPM_SRC_MASK */ |
| 204 | mmio_write_32(SPM_SRC_MASK, |
| 205 | ((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) | |
| 206 | ((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) | |
| 207 | ((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) | |
| 208 | ((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) | |
| 209 | ((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) | |
| 210 | ((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) | |
| 211 | ((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) | |
| 212 | ((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) | |
| 213 | ((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) | |
| 214 | ((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) | |
| 215 | ((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) | |
| 216 | ((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) | |
| 217 | ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | |
| 218 | ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | |
| 219 | ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) | |
| 220 | ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) | |
| 221 | ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) | |
| 222 | ((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) | |
| 223 | ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) | |
| 224 | ((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) | |
| 225 | ((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) | |
| 226 | ((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) | |
| 227 | ((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) | |
| 228 | ((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) | |
| 229 | ((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) | |
| 230 | ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) | |
| 231 | ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) | |
| 232 | ((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) | |
| 233 | ((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) | |
| 234 | ((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) | |
| 235 | ((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) | |
| 236 | ((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31)); |
| 237 | |
| 238 | /* SPM_SRC2_MASK */ |
| 239 | mmio_write_32(SPM_SRC2_MASK, |
| 240 | ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) | |
| 241 | ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) | |
| 242 | ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) | |
| 243 | ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) | |
| 244 | ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) | |
| 245 | ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) | |
| 246 | ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) | |
| 247 | ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | |
| 248 | ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) | |
| 249 | ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) | |
| 250 | ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) | |
| 251 | ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | |
| 252 | ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) | |
| 253 | ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) | |
| 254 | ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) | |
| 255 | ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) | |
| 256 | ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) | |
| 257 | ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) | |
| 258 | ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) | |
| 259 | ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) | |
| 260 | ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) | |
| 261 | ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) | |
| 262 | ((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) | |
| 263 | ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) | |
| 264 | ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) | |
| 265 | ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) | |
| 266 | ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) | |
| 267 | ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) | |
| 268 | ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) | |
| 269 | ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) | |
| 270 | ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) | |
| 271 | ((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31)); |
| 272 | |
| 273 | /* SPM_SRC3_MASK */ |
| 274 | mmio_write_32(SPM_SRC3_MASK, |
| 275 | ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) | |
| 276 | ((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) | |
| 277 | ((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) | |
| 278 | ((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) | |
| 279 | ((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) | |
| 280 | ((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) | |
| 281 | ((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) | |
| 282 | ((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) | |
| 283 | ((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) | |
| 284 | ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) | |
| 285 | ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) | |
| 286 | ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) | |
| 287 | ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) | |
| 288 | ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) | |
| 289 | ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) | |
| 290 | ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) | |
| 291 | ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) | |
| 292 | ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) | |
| 293 | ((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) | |
| 294 | ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) | |
| 295 | ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) | |
| 296 | ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) | |
| 297 | ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) | |
| 298 | ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) | |
| 299 | ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) | |
| 300 | ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) | |
| 301 | ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) | |
| 302 | ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) | |
| 303 | ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31)); |
| 304 | |
| 305 | /* SPM_SRC4_MASK */ |
| 306 | mmio_write_32(SPM_SRC4_MASK, |
| 307 | ((pwrctrl->ccif_event_mask_b & 0xffff) << 0) | |
| 308 | ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) | |
| 309 | ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) | |
| 310 | ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) | |
| 311 | ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) | |
| 312 | ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) | |
| 313 | ((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) | |
| 314 | ((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) | |
| 315 | ((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) | |
| 316 | ((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) | |
| 317 | ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) | |
| 318 | ((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) | |
| 319 | ((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27)); |
| 320 | |
| 321 | /* SPM_SRC5_MASK */ |
| 322 | mmio_write_32(SPM_SRC5_MASK, |
| 323 | ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | |
| 324 | ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) | |
| 325 | ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) | |
| 326 | ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) | |
| 327 | ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) | |
| 328 | ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) | |
| 329 | ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) | |
| 330 | ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) | |
| 331 | ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) | |
| 332 | ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) | |
| 333 | ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) | |
| 334 | ((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27)); |
| 335 | |
| 336 | /* SPM_WAKEUP_EVENT_MASK */ |
| 337 | mmio_write_32(SPM_WAKEUP_EVENT_MASK, |
| 338 | ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); |
| 339 | |
| 340 | /* SPM_WAKEUP_EVENT_EXT_MASK */ |
| 341 | mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, |
| 342 | ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); |
| 343 | |
| 344 | /* Auto-gen End */ |
| 345 | } |
| 346 | |
| 347 | void __spm_disable_pcm_timer(void) |
| 348 | { |
| 349 | mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); |
| 350 | } |
| 351 | |
| 352 | void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) |
| 353 | { |
| 354 | uint32_t val, mask; |
| 355 | |
| 356 | /* toggle event counter clear */ |
| 357 | mmio_setbits_32(PCM_CON1, |
| 358 | SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); |
| 359 | |
| 360 | /* toggle for reset SYS TIMER start point */ |
| 361 | mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); |
| 362 | |
| 363 | if (pwrctrl->timer_val_cust == 0U) { |
| 364 | val = pwrctrl->timer_val; |
| 365 | } else { |
| 366 | val = pwrctrl->timer_val_cust; |
| 367 | } |
| 368 | |
| 369 | mmio_write_32(PCM_TIMER_VAL, val); |
| 370 | mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); |
| 371 | |
| 372 | /* unmask AP wakeup source */ |
| 373 | if (pwrctrl->wake_src_cust == 0U) { |
| 374 | mask = pwrctrl->wake_src; |
| 375 | } else { |
| 376 | mask = pwrctrl->wake_src_cust; |
| 377 | } |
| 378 | |
| 379 | if (pwrctrl->reg_csyspwrreq_mask != 0U) { |
| 380 | mask &= ~R12_CSYSPWREQ_B; |
| 381 | } |
| 382 | |
| 383 | mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); |
| 384 | |
| 385 | /* unmask SPM ISR (keep TWAM setting) */ |
| 386 | mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX); |
| 387 | |
| 388 | /* toggle event counter clear */ |
| 389 | mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, |
| 390 | SPM_REGWR_CFG_KEY); |
| 391 | /* toggle for reset SYS TIMER start point */ |
| 392 | mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); |
| 393 | } |
| 394 | |
| 395 | void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) |
| 396 | { |
| 397 | /* set PCM flags and data */ |
| 398 | if (pwrctrl->pcm_flags_cust_clr != 0U) { |
| 399 | pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; |
| 400 | } |
| 401 | |
| 402 | if (pwrctrl->pcm_flags_cust_set != 0U) { |
| 403 | pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; |
| 404 | } |
| 405 | |
| 406 | if (pwrctrl->pcm_flags1_cust_clr != 0U) { |
| 407 | pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; |
| 408 | } |
| 409 | |
| 410 | if (pwrctrl->pcm_flags1_cust_set != 0U) { |
| 411 | pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; |
| 412 | } |
| 413 | |
| 414 | mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags); |
| 415 | mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1); |
| 416 | mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags); |
| 417 | mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1); |
| 418 | } |
| 419 | |
| 420 | void __spm_get_wakeup_status(struct wake_status *wakesta, |
| 421 | unsigned int ext_status) |
| 422 | { |
| 423 | wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); |
| 424 | wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER); |
| 425 | wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA); |
| 426 | wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0); |
| 427 | wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1); |
| 428 | wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2); |
| 429 | wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3); |
| 430 | wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4); |
| 431 | wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); |
| 432 | wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); |
| 433 | |
| 434 | if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) { |
| 435 | wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE | |
| 436 | SPM_DBG_DEBUG_IDX_DDREN_SLEEP); |
| 437 | mmio_write_32(PCM_WDT_LATCH_SPARE_0, |
| 438 | wakesta->tr.comm.debug_flag); |
| 439 | } |
| 440 | |
| 441 | wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); |
| 442 | wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); |
| 443 | |
| 444 | /* record below spm info for debug */ |
| 445 | wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT); |
| 446 | wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA); |
| 447 | wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); |
| 448 | wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); |
| 449 | wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA); |
| 450 | wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA); |
| 451 | wakesta->src_req = mmio_read_32(SPM_SRC_REQ); |
| 452 | |
| 453 | /* backup of SPM_WAKEUP_MISC */ |
| 454 | wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); |
| 455 | |
| 456 | /* get sleep time, backup of PCM_TIMER_OUT */ |
| 457 | wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER); |
| 458 | |
| 459 | /* get other SYS and co-clock status */ |
| 460 | wakesta->r13 = mmio_read_32(PCM_REG13_DATA); |
| 461 | wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA); |
| 462 | wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0); |
| 463 | wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1); |
| 464 | wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2); |
| 465 | wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3); |
| 466 | wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4); |
| 467 | |
| 468 | /* get HW CG check status */ |
| 469 | wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA); |
| 470 | |
| 471 | /* get debug flag for PCM execution check */ |
| 472 | wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); |
| 473 | wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); |
| 474 | |
| 475 | /* get backup SW flag status */ |
| 476 | wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); |
| 477 | wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); |
| 478 | |
| 479 | wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2); |
| 480 | wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3); |
| 481 | wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4); |
| 482 | wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5); |
| 483 | wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6); |
| 484 | |
| 485 | /* get ISR status */ |
| 486 | wakesta->isr = mmio_read_32(SPM_IRQ_STA); |
| 487 | |
| 488 | /* get SW flag status */ |
| 489 | wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0); |
| 490 | wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1); |
| 491 | |
| 492 | /* get CLK SETTLE */ |
| 493 | wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE); |
| 494 | |
| 495 | /* check abort */ |
| 496 | wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) | |
| 497 | (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1); |
| 498 | } |
| 499 | |
| 500 | void __spm_clean_after_wakeup(void) |
| 501 | { |
| 502 | mmio_write_32(SPM_BK_WAKE_EVENT, |
| 503 | mmio_read_32(SPM_WAKEUP_STA) | |
| 504 | mmio_read_32(SPM_BK_WAKE_EVENT)); |
| 505 | mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); |
| 506 | |
| 507 | /* |
| 508 | * clean wakeup event raw status (for edge trigger event) |
| 509 | * bit[28] for cpu wake up event |
| 510 | */ |
| 511 | mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK); |
| 512 | |
| 513 | /* clean ISR status (except TWAM) */ |
| 514 | mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); |
| 515 | mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); |
| 516 | mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); |
| 517 | } |
| 518 | |
| 519 | void __spm_set_pcm_wdt(int en) |
| 520 | { |
| 521 | mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, |
| 522 | SPM_REGWR_CFG_KEY); |
| 523 | |
| 524 | if (en == 1) { |
| 525 | mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, |
| 526 | SPM_REGWR_CFG_KEY); |
| 527 | |
| 528 | if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) { |
| 529 | mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); |
| 530 | } |
| 531 | |
| 532 | mmio_write_32(PCM_WDT_VAL, |
| 533 | mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); |
| 534 | mmio_setbits_32(PCM_CON1, |
| 535 | SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); |
| 536 | } |
| 537 | } |
| 538 | |
| 539 | void __spm_send_cpu_wakeup_event(void) |
| 540 | { |
| 541 | /* SPM will clear SPM_CPU_WAKEUP_EVENT */ |
| 542 | mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); |
| 543 | } |
| 544 | |
| 545 | void __spm_ext_int_wakeup_req_clr(void) |
| 546 | { |
| 547 | mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR)); |
| 548 | |
| 549 | /* Clear spm2mcupm wakeup interrupt status */ |
| 550 | mmio_write_32(SPM2MCUPM_CON, 0); |
| 551 | } |
| 552 | |
| 553 | void __spm_xo_soc_bblpm(int en) |
| 554 | { |
| 555 | if (en == 1) { |
| 556 | mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG, |
| 557 | RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC); |
| 558 | assert(mt_spm_bblpm_cnt == 0); |
| 559 | mt_spm_bblpm_cnt += 1; |
| 560 | } else { |
| 561 | mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG, |
| 562 | RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM); |
| 563 | mt_spm_bblpm_cnt -= 1; |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | void __spm_hw_s1_state_monitor(int en, unsigned int *status) |
| 568 | { |
| 569 | unsigned int reg; |
| 570 | |
| 571 | reg = mmio_read_32(SPM_ACK_CHK_CON_3); |
| 572 | |
| 573 | if (en == 1) { |
| 574 | reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL; |
| 575 | mmio_write_32(SPM_ACK_CHK_CON_3, reg); |
| 576 | reg |= SPM_ACK_CHK_3_CON_EN; |
| 577 | mmio_write_32(SPM_ACK_CHK_CON_3, reg); |
| 578 | } else { |
| 579 | if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) && |
| 580 | (status != NULL)) { |
| 581 | *status |= SPM_INTERNAL_STATUS_HW_S1; |
| 582 | } |
| 583 | |
| 584 | mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, |
| 585 | SPM_ACK_CHK_3_CON_HW_MODE_TRIG | |
| 586 | SPM_ACK_CHK_3_CON_CLR_ALL); |
| 587 | } |
| 588 | } |