| Gabriel Fernandez | 1308d75 | 2020-03-11 11:30:34 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP13_RCC_H |
| 8 | #define STM32MP13_RCC_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | #define RCC_SECCFGR U(0X0) |
| 13 | #define RCC_MP_SREQSETR U(0X100) |
| 14 | #define RCC_MP_SREQCLRR U(0X104) |
| 15 | #define RCC_MP_APRSTCR U(0X108) |
| 16 | #define RCC_MP_APRSTSR U(0X10C) |
| 17 | #define RCC_PWRLPDLYCR U(0X110) |
| 18 | #define RCC_MP_GRSTCSETR U(0X114) |
| 19 | #define RCC_BR_RSTSCLRR U(0X118) |
| 20 | #define RCC_MP_RSTSSETR U(0X11C) |
| 21 | #define RCC_MP_RSTSCLRR U(0X120) |
| 22 | #define RCC_MP_IWDGFZSETR U(0X124) |
| 23 | #define RCC_MP_IWDGFZCLRR U(0X128) |
| 24 | #define RCC_MP_CIER U(0X200) |
| 25 | #define RCC_MP_CIFR U(0X204) |
| 26 | #define RCC_BDCR U(0X400) |
| 27 | #define RCC_RDLSICR U(0X404) |
| 28 | #define RCC_OCENSETR U(0X420) |
| 29 | #define RCC_OCENCLRR U(0X424) |
| 30 | #define RCC_OCRDYR U(0X428) |
| 31 | #define RCC_HSICFGR U(0X440) |
| 32 | #define RCC_CSICFGR U(0X444) |
| 33 | #define RCC_MCO1CFGR U(0X460) |
| 34 | #define RCC_MCO2CFGR U(0X464) |
| 35 | #define RCC_DBGCFGR U(0X468) |
| 36 | #define RCC_RCK12SELR U(0X480) |
| 37 | #define RCC_RCK3SELR U(0X484) |
| 38 | #define RCC_RCK4SELR U(0X488) |
| 39 | #define RCC_PLL1CR U(0X4A0) |
| 40 | #define RCC_PLL1CFGR1 U(0X4A4) |
| 41 | #define RCC_PLL1CFGR2 U(0X4A8) |
| 42 | #define RCC_PLL1FRACR U(0X4AC) |
| 43 | #define RCC_PLL1CSGR U(0X4B0) |
| 44 | #define RCC_PLL2CR U(0X4D0) |
| 45 | #define RCC_PLL2CFGR1 U(0X4D4) |
| 46 | #define RCC_PLL2CFGR2 U(0X4D8) |
| 47 | #define RCC_PLL2FRACR U(0X4DC) |
| 48 | #define RCC_PLL2CSGR U(0X4E0) |
| 49 | #define RCC_PLL3CR U(0X500) |
| 50 | #define RCC_PLL3CFGR1 U(0X504) |
| 51 | #define RCC_PLL3CFGR2 U(0X508) |
| 52 | #define RCC_PLL3FRACR U(0X50C) |
| 53 | #define RCC_PLL3CSGR U(0X510) |
| 54 | #define RCC_PLL4CR U(0X520) |
| 55 | #define RCC_PLL4CFGR1 U(0X524) |
| 56 | #define RCC_PLL4CFGR2 U(0X528) |
| 57 | #define RCC_PLL4FRACR U(0X52C) |
| 58 | #define RCC_PLL4CSGR U(0X530) |
| 59 | #define RCC_MPCKSELR U(0X540) |
| 60 | #define RCC_ASSCKSELR U(0X544) |
| 61 | #define RCC_MSSCKSELR U(0X548) |
| 62 | #define RCC_CPERCKSELR U(0X54C) |
| 63 | #define RCC_RTCDIVR U(0X560) |
| 64 | #define RCC_MPCKDIVR U(0X564) |
| 65 | #define RCC_AXIDIVR U(0X568) |
| 66 | #define RCC_MLAHBDIVR U(0X56C) |
| 67 | #define RCC_APB1DIVR U(0X570) |
| 68 | #define RCC_APB2DIVR U(0X574) |
| 69 | #define RCC_APB3DIVR U(0X578) |
| 70 | #define RCC_APB4DIVR U(0X57C) |
| 71 | #define RCC_APB5DIVR U(0X580) |
| 72 | #define RCC_APB6DIVR U(0X584) |
| 73 | #define RCC_TIMG1PRER U(0X5A0) |
| 74 | #define RCC_TIMG2PRER U(0X5A4) |
| 75 | #define RCC_TIMG3PRER U(0X5A8) |
| 76 | #define RCC_DDRITFCR U(0X5C0) |
| 77 | #define RCC_I2C12CKSELR U(0X600) |
| 78 | #define RCC_I2C345CKSELR U(0X604) |
| 79 | #define RCC_SPI2S1CKSELR U(0X608) |
| 80 | #define RCC_SPI2S23CKSELR U(0X60C) |
| 81 | #define RCC_SPI45CKSELR U(0X610) |
| 82 | #define RCC_UART12CKSELR U(0X614) |
| 83 | #define RCC_UART35CKSELR U(0X618) |
| 84 | #define RCC_UART4CKSELR U(0X61C) |
| 85 | #define RCC_UART6CKSELR U(0X620) |
| 86 | #define RCC_UART78CKSELR U(0X624) |
| 87 | #define RCC_LPTIM1CKSELR U(0X628) |
| 88 | #define RCC_LPTIM23CKSELR U(0X62C) |
| 89 | #define RCC_LPTIM45CKSELR U(0X630) |
| 90 | #define RCC_SAI1CKSELR U(0X634) |
| 91 | #define RCC_SAI2CKSELR U(0X638) |
| 92 | #define RCC_FDCANCKSELR U(0X63C) |
| 93 | #define RCC_SPDIFCKSELR U(0X640) |
| 94 | #define RCC_ADC12CKSELR U(0X644) |
| 95 | #define RCC_SDMMC12CKSELR U(0X648) |
| 96 | #define RCC_ETH12CKSELR U(0X64C) |
| 97 | #define RCC_USBCKSELR U(0X650) |
| 98 | #define RCC_QSPICKSELR U(0X654) |
| 99 | #define RCC_FMCCKSELR U(0X658) |
| 100 | #define RCC_RNG1CKSELR U(0X65C) |
| 101 | #define RCC_STGENCKSELR U(0X660) |
| 102 | #define RCC_DCMIPPCKSELR U(0X664) |
| 103 | #define RCC_SAESCKSELR U(0X668) |
| 104 | #define RCC_APB1RSTSETR U(0X6A0) |
| 105 | #define RCC_APB1RSTCLRR U(0X6A4) |
| 106 | #define RCC_APB2RSTSETR U(0X6A8) |
| 107 | #define RCC_APB2RSTCLRR U(0X6AC) |
| 108 | #define RCC_APB3RSTSETR U(0X6B0) |
| 109 | #define RCC_APB3RSTCLRR U(0X6B4) |
| 110 | #define RCC_APB4RSTSETR U(0X6B8) |
| 111 | #define RCC_APB4RSTCLRR U(0X6BC) |
| 112 | #define RCC_APB5RSTSETR U(0X6C0) |
| 113 | #define RCC_APB5RSTCLRR U(0X6C4) |
| 114 | #define RCC_APB6RSTSETR U(0X6C8) |
| 115 | #define RCC_APB6RSTCLRR U(0X6CC) |
| 116 | #define RCC_AHB2RSTSETR U(0X6D0) |
| 117 | #define RCC_AHB2RSTCLRR U(0X6D4) |
| 118 | #define RCC_AHB4RSTSETR U(0X6E0) |
| 119 | #define RCC_AHB4RSTCLRR U(0X6E4) |
| 120 | #define RCC_AHB5RSTSETR U(0X6E8) |
| 121 | #define RCC_AHB5RSTCLRR U(0X6EC) |
| 122 | #define RCC_AHB6RSTSETR U(0X6F0) |
| 123 | #define RCC_AHB6RSTCLRR U(0X6F4) |
| 124 | #define RCC_MP_APB1ENSETR U(0X700) |
| 125 | #define RCC_MP_APB1ENCLRR U(0X704) |
| 126 | #define RCC_MP_APB2ENSETR U(0X708) |
| 127 | #define RCC_MP_APB2ENCLRR U(0X70C) |
| 128 | #define RCC_MP_APB3ENSETR U(0X710) |
| 129 | #define RCC_MP_APB3ENCLRR U(0X714) |
| 130 | #define RCC_MP_S_APB3ENSETR U(0X718) |
| 131 | #define RCC_MP_S_APB3ENCLRR U(0X71C) |
| 132 | #define RCC_MP_NS_APB3ENSETR U(0X720) |
| 133 | #define RCC_MP_NS_APB3ENCLRR U(0X724) |
| 134 | #define RCC_MP_APB4ENSETR U(0X728) |
| 135 | #define RCC_MP_APB4ENCLRR U(0X72C) |
| 136 | #define RCC_MP_S_APB4ENSETR U(0X730) |
| 137 | #define RCC_MP_S_APB4ENCLRR U(0X734) |
| 138 | #define RCC_MP_NS_APB4ENSETR U(0X738) |
| 139 | #define RCC_MP_NS_APB4ENCLRR U(0X73C) |
| 140 | #define RCC_MP_APB5ENSETR U(0X740) |
| 141 | #define RCC_MP_APB5ENCLRR U(0X744) |
| 142 | #define RCC_MP_APB6ENSETR U(0X748) |
| 143 | #define RCC_MP_APB6ENCLRR U(0X74C) |
| 144 | #define RCC_MP_AHB2ENSETR U(0X750) |
| 145 | #define RCC_MP_AHB2ENCLRR U(0X754) |
| 146 | #define RCC_MP_AHB4ENSETR U(0X760) |
| 147 | #define RCC_MP_AHB4ENCLRR U(0X764) |
| 148 | #define RCC_MP_S_AHB4ENSETR U(0X768) |
| 149 | #define RCC_MP_S_AHB4ENCLRR U(0X76C) |
| 150 | #define RCC_MP_NS_AHB4ENSETR U(0X770) |
| 151 | #define RCC_MP_NS_AHB4ENCLRR U(0X774) |
| 152 | #define RCC_MP_AHB5ENSETR U(0X778) |
| 153 | #define RCC_MP_AHB5ENCLRR U(0X77C) |
| 154 | #define RCC_MP_AHB6ENSETR U(0X780) |
| 155 | #define RCC_MP_AHB6ENCLRR U(0X784) |
| 156 | #define RCC_MP_S_AHB6ENSETR U(0X788) |
| 157 | #define RCC_MP_S_AHB6ENCLRR U(0X78C) |
| 158 | #define RCC_MP_NS_AHB6ENSETR U(0X790) |
| 159 | #define RCC_MP_NS_AHB6ENCLRR U(0X794) |
| 160 | #define RCC_MP_APB1LPENSETR U(0X800) |
| 161 | #define RCC_MP_APB1LPENCLRR U(0X804) |
| 162 | #define RCC_MP_APB2LPENSETR U(0X808) |
| 163 | #define RCC_MP_APB2LPENCLRR U(0X80C) |
| 164 | #define RCC_MP_APB3LPENSETR U(0X810) |
| 165 | #define RCC_MP_APB3LPENCLRR U(0X814) |
| 166 | #define RCC_MP_S_APB3LPENSETR U(0X818) |
| 167 | #define RCC_MP_S_APB3LPENCLRR U(0X81C) |
| 168 | #define RCC_MP_NS_APB3LPENSETR U(0X820) |
| 169 | #define RCC_MP_NS_APB3LPENCLRR U(0X824) |
| 170 | #define RCC_MP_APB4LPENSETR U(0X828) |
| 171 | #define RCC_MP_APB4LPENCLRR U(0X82C) |
| 172 | #define RCC_MP_S_APB4LPENSETR U(0X830) |
| 173 | #define RCC_MP_S_APB4LPENCLRR U(0X834) |
| 174 | #define RCC_MP_NS_APB4LPENSETR U(0X838) |
| 175 | #define RCC_MP_NS_APB4LPENCLRR U(0X83C) |
| 176 | #define RCC_MP_APB5LPENSETR U(0X840) |
| 177 | #define RCC_MP_APB5LPENCLRR U(0X844) |
| 178 | #define RCC_MP_APB6LPENSETR U(0X848) |
| 179 | #define RCC_MP_APB6LPENCLRR U(0X84C) |
| 180 | #define RCC_MP_AHB2LPENSETR U(0X850) |
| 181 | #define RCC_MP_AHB2LPENCLRR U(0X854) |
| 182 | #define RCC_MP_AHB4LPENSETR U(0X858) |
| 183 | #define RCC_MP_AHB4LPENCLRR U(0X85C) |
| 184 | #define RCC_MP_S_AHB4LPENSETR U(0X868) |
| 185 | #define RCC_MP_S_AHB4LPENCLRR U(0X86C) |
| 186 | #define RCC_MP_NS_AHB4LPENSETR U(0X870) |
| 187 | #define RCC_MP_NS_AHB4LPENCLRR U(0X874) |
| 188 | #define RCC_MP_AHB5LPENSETR U(0X878) |
| 189 | #define RCC_MP_AHB5LPENCLRR U(0X87C) |
| 190 | #define RCC_MP_AHB6LPENSETR U(0X880) |
| 191 | #define RCC_MP_AHB6LPENCLRR U(0X884) |
| 192 | #define RCC_MP_S_AHB6LPENSETR U(0X888) |
| 193 | #define RCC_MP_S_AHB6LPENCLRR U(0X88C) |
| 194 | #define RCC_MP_NS_AHB6LPENSETR U(0X890) |
| 195 | #define RCC_MP_NS_AHB6LPENCLRR U(0X894) |
| 196 | #define RCC_MP_S_AXIMLPENSETR U(0X898) |
| 197 | #define RCC_MP_S_AXIMLPENCLRR U(0X89C) |
| 198 | #define RCC_MP_NS_AXIMLPENSETR U(0X8A0) |
| 199 | #define RCC_MP_NS_AXIMLPENCLRR U(0X8A4) |
| 200 | #define RCC_MP_MLAHBLPENSETR U(0X8A8) |
| 201 | #define RCC_MP_MLAHBLPENCLRR U(0X8AC) |
| 202 | #define RCC_APB3SECSR U(0X8C0) |
| 203 | #define RCC_APB4SECSR U(0X8C4) |
| 204 | #define RCC_APB5SECSR U(0X8C8) |
| 205 | #define RCC_APB6SECSR U(0X8CC) |
| 206 | #define RCC_AHB2SECSR U(0X8D0) |
| 207 | #define RCC_AHB4SECSR U(0X8D4) |
| 208 | #define RCC_AHB5SECSR U(0X8D8) |
| 209 | #define RCC_AHB6SECSR U(0X8DC) |
| 210 | #define RCC_VERR U(0XFF4) |
| 211 | #define RCC_IDR U(0XFF8) |
| 212 | #define RCC_SIDR U(0XFFC) |
| 213 | |
| 214 | /* RCC_SECCFGR register fields */ |
| 215 | #define RCC_SECCFGR_HSISEC BIT(0) |
| 216 | #define RCC_SECCFGR_CSISEC BIT(1) |
| 217 | #define RCC_SECCFGR_HSESEC BIT(2) |
| 218 | #define RCC_SECCFGR_LSISEC BIT(3) |
| 219 | #define RCC_SECCFGR_LSESEC BIT(4) |
| 220 | #define RCC_SECCFGR_PLL12SEC BIT(8) |
| 221 | #define RCC_SECCFGR_PLL3SEC BIT(9) |
| 222 | #define RCC_SECCFGR_PLL4SEC BIT(10) |
| 223 | #define RCC_SECCFGR_MPUSEC BIT(11) |
| 224 | #define RCC_SECCFGR_AXISEC BIT(12) |
| 225 | #define RCC_SECCFGR_MLAHBSEC BIT(13) |
| 226 | #define RCC_SECCFGR_APB3DIVSEC BIT(16) |
| 227 | #define RCC_SECCFGR_APB4DIVSEC BIT(17) |
| 228 | #define RCC_SECCFGR_APB5DIVSEC BIT(18) |
| 229 | #define RCC_SECCFGR_APB6DIVSEC BIT(19) |
| 230 | #define RCC_SECCFGR_TIMG3SEC BIT(20) |
| 231 | #define RCC_SECCFGR_CPERSEC BIT(21) |
| 232 | #define RCC_SECCFGR_MCO1SEC BIT(22) |
| 233 | #define RCC_SECCFGR_MCO2SEC BIT(23) |
| 234 | #define RCC_SECCFGR_STPSEC BIT(24) |
| 235 | #define RCC_SECCFGR_RSTSEC BIT(25) |
| 236 | #define RCC_SECCFGR_PWRSEC BIT(31) |
| 237 | |
| 238 | /* RCC_MP_SREQSETR register fields */ |
| 239 | #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) |
| 240 | |
| 241 | /* RCC_MP_SREQCLRR register fields */ |
| 242 | #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) |
| 243 | |
| 244 | /* RCC_MP_APRSTCR register fields */ |
| 245 | #define RCC_MP_APRSTCR_RDCTLEN BIT(0) |
| 246 | #define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) |
| 247 | #define RCC_MP_APRSTCR_RSTTO_SHIFT 8 |
| 248 | |
| 249 | /* RCC_MP_APRSTSR register fields */ |
| 250 | #define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) |
| 251 | #define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 |
| 252 | |
| 253 | /* RCC_PWRLPDLYCR register fields */ |
| 254 | #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) |
| 255 | #define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 |
| 256 | |
| 257 | /* RCC_MP_GRSTCSETR register fields */ |
| 258 | #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) |
| 259 | #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) |
| 260 | |
| 261 | /* RCC_BR_RSTSCLRR register fields */ |
| 262 | #define RCC_BR_RSTSCLRR_PORRSTF BIT(0) |
| 263 | #define RCC_BR_RSTSCLRR_BORRSTF BIT(1) |
| 264 | #define RCC_BR_RSTSCLRR_PADRSTF BIT(2) |
| 265 | #define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) |
| 266 | #define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) |
| 267 | #define RCC_BR_RSTSCLRR_VCPURSTF BIT(5) |
| 268 | #define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) |
| 269 | #define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) |
| 270 | #define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) |
| 271 | #define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) |
| 272 | |
| 273 | /* RCC_MP_RSTSSETR register fields */ |
| 274 | #define RCC_MP_RSTSSETR_PORRSTF BIT(0) |
| 275 | #define RCC_MP_RSTSSETR_BORRSTF BIT(1) |
| 276 | #define RCC_MP_RSTSSETR_PADRSTF BIT(2) |
| 277 | #define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) |
| 278 | #define RCC_MP_RSTSSETR_VCORERSTF BIT(4) |
| 279 | #define RCC_MP_RSTSSETR_VCPURSTF BIT(5) |
| 280 | #define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) |
| 281 | #define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) |
| 282 | #define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) |
| 283 | #define RCC_MP_RSTSSETR_STP2RSTF BIT(10) |
| 284 | #define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) |
| 285 | #define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) |
| 286 | #define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) |
| 287 | #define RCC_MP_RSTSSETR_SPARE BIT(15) |
| 288 | |
| 289 | /* RCC_MP_RSTSCLRR register fields */ |
| 290 | #define RCC_MP_RSTSCLRR_PORRSTF BIT(0) |
| 291 | #define RCC_MP_RSTSCLRR_BORRSTF BIT(1) |
| 292 | #define RCC_MP_RSTSCLRR_PADRSTF BIT(2) |
| 293 | #define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) |
| 294 | #define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) |
| 295 | #define RCC_MP_RSTSCLRR_VCPURSTF BIT(5) |
| 296 | #define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) |
| 297 | #define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) |
| 298 | #define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) |
| 299 | #define RCC_MP_RSTSCLRR_STP2RSTF BIT(10) |
| 300 | #define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) |
| 301 | #define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) |
| 302 | #define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) |
| 303 | #define RCC_MP_RSTSCLRR_SPARE BIT(15) |
| 304 | |
| 305 | /* RCC_MP_IWDGFZSETR register fields */ |
| 306 | #define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) |
| 307 | #define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) |
| 308 | |
| 309 | /* RCC_MP_IWDGFZCLRR register fields */ |
| 310 | #define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) |
| 311 | #define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) |
| 312 | |
| 313 | /* RCC_MP_CIER register fields */ |
| 314 | #define RCC_MP_CIER_LSIRDYIE BIT(0) |
| 315 | #define RCC_MP_CIER_LSERDYIE BIT(1) |
| 316 | #define RCC_MP_CIER_HSIRDYIE BIT(2) |
| 317 | #define RCC_MP_CIER_HSERDYIE BIT(3) |
| 318 | #define RCC_MP_CIER_CSIRDYIE BIT(4) |
| 319 | #define RCC_MP_CIER_PLL1DYIE BIT(8) |
| 320 | #define RCC_MP_CIER_PLL2DYIE BIT(9) |
| 321 | #define RCC_MP_CIER_PLL3DYIE BIT(10) |
| 322 | #define RCC_MP_CIER_PLL4DYIE BIT(11) |
| 323 | #define RCC_MP_CIER_LSECSSIE BIT(16) |
| 324 | #define RCC_MP_CIER_WKUPIE BIT(20) |
| 325 | |
| 326 | /* RCC_MP_CIFR register fields */ |
| 327 | #define RCC_MP_CIFR_LSIRDYF BIT(0) |
| 328 | #define RCC_MP_CIFR_LSERDYF BIT(1) |
| 329 | #define RCC_MP_CIFR_HSIRDYF BIT(2) |
| 330 | #define RCC_MP_CIFR_HSERDYF BIT(3) |
| 331 | #define RCC_MP_CIFR_CSIRDYF BIT(4) |
| 332 | #define RCC_MP_CIFR_PLL1DYF BIT(8) |
| 333 | #define RCC_MP_CIFR_PLL2DYF BIT(9) |
| 334 | #define RCC_MP_CIFR_PLL3DYF BIT(10) |
| 335 | #define RCC_MP_CIFR_PLL4DYF BIT(11) |
| 336 | #define RCC_MP_CIFR_LSECSSF BIT(16) |
| 337 | #define RCC_MP_CIFR_WKUPF BIT(20) |
| 338 | |
| 339 | /* RCC_BDCR register fields */ |
| 340 | #define RCC_BDCR_LSEON BIT(0) |
| 341 | #define RCC_BDCR_LSEBYP BIT(1) |
| 342 | #define RCC_BDCR_LSERDY BIT(2) |
| 343 | #define RCC_BDCR_DIGBYP BIT(3) |
| 344 | #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) |
| 345 | #define RCC_BDCR_LSEDRV_SHIFT 4 |
| 346 | #define RCC_BDCR_LSECSSON BIT(8) |
| 347 | #define RCC_BDCR_LSECSSD BIT(9) |
| 348 | #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) |
| 349 | #define RCC_BDCR_RTCSRC_SHIFT 16 |
| 350 | #define RCC_BDCR_RTCCKEN BIT(20) |
| 351 | #define RCC_BDCR_VSWRST BIT(31) |
| 352 | |
| 353 | #define RCC_BDCR_LSEBYP_BIT 1 |
| 354 | #define RCC_BDCR_LSERDY_BIT 2 |
| 355 | #define RCC_BDCR_DIGBYP_BIT 3 |
| 356 | #define RCC_BDCR_LSECSSON_BIT 8 |
| 357 | |
| 358 | #define RCC_BDCR_LSEDRV_WIDTH 2 |
| 359 | |
| 360 | /* RCC_RDLSICR register fields */ |
| 361 | #define RCC_RDLSICR_LSION BIT(0) |
| 362 | #define RCC_RDLSICR_LSIRDY BIT(1) |
| 363 | #define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) |
| 364 | #define RCC_RDLSICR_MRD_SHIFT 16 |
| 365 | #define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) |
| 366 | #define RCC_RDLSICR_EADLY_SHIFT 24 |
| 367 | #define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) |
| 368 | #define RCC_RDLSICR_SPARE_SHIFT 27 |
| 369 | |
| 370 | #define RCC_RDLSICR_LSIRDY_BIT 1 |
| 371 | |
| 372 | /* RCC_OCENSETR register fields */ |
| 373 | #define RCC_OCENSETR_HSION BIT(0) |
| 374 | #define RCC_OCENSETR_HSIKERON BIT(1) |
| 375 | #define RCC_OCENSETR_CSION BIT(4) |
| 376 | #define RCC_OCENSETR_CSIKERON BIT(5) |
| 377 | #define RCC_OCENSETR_DIGBYP BIT(7) |
| 378 | #define RCC_OCENSETR_HSEON BIT(8) |
| 379 | #define RCC_OCENSETR_HSEKERON BIT(9) |
| 380 | #define RCC_OCENSETR_HSEBYP BIT(10) |
| 381 | #define RCC_OCENSETR_HSECSSON BIT(11) |
| 382 | |
| 383 | #define RCC_OCENR_DIGBYP_BIT 7 |
| 384 | #define RCC_OCENR_HSEBYP_BIT 10 |
| 385 | #define RCC_OCENR_HSECSSON_BIT 11 |
| 386 | |
| 387 | /* RCC_OCENCLRR register fields */ |
| 388 | #define RCC_OCENCLRR_HSION BIT(0) |
| 389 | #define RCC_OCENCLRR_HSIKERON BIT(1) |
| 390 | #define RCC_OCENCLRR_CSION BIT(4) |
| 391 | #define RCC_OCENCLRR_CSIKERON BIT(5) |
| 392 | #define RCC_OCENCLRR_DIGBYP BIT(7) |
| 393 | #define RCC_OCENCLRR_HSEON BIT(8) |
| 394 | #define RCC_OCENCLRR_HSEKERON BIT(9) |
| 395 | #define RCC_OCENCLRR_HSEBYP BIT(10) |
| 396 | |
| 397 | /* RCC_OCRDYR register fields */ |
| 398 | #define RCC_OCRDYR_HSIRDY BIT(0) |
| 399 | #define RCC_OCRDYR_HSIDIVRDY BIT(2) |
| 400 | #define RCC_OCRDYR_CSIRDY BIT(4) |
| 401 | #define RCC_OCRDYR_HSERDY BIT(8) |
| 402 | #define RCC_OCRDYR_MPUCKRDY BIT(23) |
| 403 | #define RCC_OCRDYR_AXICKRDY BIT(24) |
| 404 | |
| 405 | #define RCC_OCRDYR_HSIRDY_BIT 0 |
| 406 | #define RCC_OCRDYR_HSIDIVRDY_BIT 2 |
| 407 | #define RCC_OCRDYR_CSIRDY_BIT 4 |
| 408 | #define RCC_OCRDYR_HSERDY_BIT 8 |
| 409 | |
| 410 | /* RCC_HSICFGR register fields */ |
| 411 | #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) |
| 412 | #define RCC_HSICFGR_HSIDIV_SHIFT 0 |
| 413 | #define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) |
| 414 | #define RCC_HSICFGR_HSITRIM_SHIFT 8 |
| 415 | #define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16) |
| 416 | #define RCC_HSICFGR_HSICAL_SHIFT 16 |
| 417 | |
| 418 | /* RCC_CSICFGR register fields */ |
| 419 | #define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) |
| 420 | #define RCC_CSICFGR_CSITRIM_SHIFT 8 |
| 421 | #define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) |
| 422 | #define RCC_CSICFGR_CSICAL_SHIFT 16 |
| 423 | |
| 424 | /* RCC_MCO1CFGR register fields */ |
| 425 | #define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) |
| 426 | #define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 |
| 427 | #define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) |
| 428 | #define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 |
| 429 | #define RCC_MCO1CFGR_MCO1ON BIT(12) |
| 430 | |
| 431 | /* RCC_MCO2CFGR register fields */ |
| 432 | #define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) |
| 433 | #define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 |
| 434 | #define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) |
| 435 | #define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 |
| 436 | #define RCC_MCO2CFGR_MCO2ON BIT(12) |
| 437 | |
| 438 | /* RCC_DBGCFGR register fields */ |
| 439 | #define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) |
| 440 | #define RCC_DBGCFGR_TRACEDIV_SHIFT 0 |
| 441 | #define RCC_DBGCFGR_DBGCKEN BIT(8) |
| 442 | #define RCC_DBGCFGR_TRACECKEN BIT(9) |
| 443 | #define RCC_DBGCFGR_DBGRST BIT(12) |
| 444 | |
| 445 | /* RCC_RCK12SELR register fields */ |
| 446 | #define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) |
| 447 | #define RCC_RCK12SELR_PLL12SRC_SHIFT 0 |
| 448 | #define RCC_RCK12SELR_PLL12SRCRDY BIT(31) |
| 449 | |
| 450 | /* RCC_RCK3SELR register fields */ |
| 451 | #define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) |
| 452 | #define RCC_RCK3SELR_PLL3SRC_SHIFT 0 |
| 453 | #define RCC_RCK3SELR_PLL3SRCRDY BIT(31) |
| 454 | |
| 455 | /* RCC_RCK4SELR register fields */ |
| 456 | #define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) |
| 457 | #define RCC_RCK4SELR_PLL4SRC_SHIFT 0 |
| 458 | #define RCC_RCK4SELR_PLL4SRCRDY BIT(31) |
| 459 | |
| 460 | /* RCC_PLL1CR register fields */ |
| 461 | #define RCC_PLL1CR_PLLON BIT(0) |
| 462 | #define RCC_PLL1CR_PLL1RDY BIT(1) |
| 463 | #define RCC_PLL1CR_SSCG_CTRL BIT(2) |
| 464 | #define RCC_PLL1CR_DIVPEN BIT(4) |
| 465 | #define RCC_PLL1CR_DIVQEN BIT(5) |
| 466 | #define RCC_PLL1CR_DIVREN BIT(6) |
| 467 | |
| 468 | /* RCC_PLL1CFGR1 register fields */ |
| 469 | #define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) |
| 470 | #define RCC_PLL1CFGR1_DIVN_SHIFT 0 |
| 471 | #define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) |
| 472 | #define RCC_PLL1CFGR1_DIVM1_SHIFT 16 |
| 473 | |
| 474 | /* RCC_PLL1CFGR2 register fields */ |
| 475 | #define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) |
| 476 | #define RCC_PLL1CFGR2_DIVP_SHIFT 0 |
| 477 | #define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) |
| 478 | #define RCC_PLL1CFGR2_DIVQ_SHIFT 8 |
| 479 | #define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) |
| 480 | #define RCC_PLL1CFGR2_DIVR_SHIFT 16 |
| 481 | |
| 482 | /* RCC_PLL1FRACR register fields */ |
| 483 | #define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) |
| 484 | #define RCC_PLL1FRACR_FRACV_SHIFT 3 |
| 485 | #define RCC_PLL1FRACR_FRACLE BIT(16) |
| 486 | |
| 487 | /* RCC_PLL1CSGR register fields */ |
| 488 | #define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) |
| 489 | #define RCC_PLL1CSGR_MOD_PER_SHIFT 0 |
| 490 | #define RCC_PLL1CSGR_TPDFN_DIS BIT(13) |
| 491 | #define RCC_PLL1CSGR_RPDFN_DIS BIT(14) |
| 492 | #define RCC_PLL1CSGR_SSCG_MODE BIT(15) |
| 493 | #define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) |
| 494 | #define RCC_PLL1CSGR_INC_STEP_SHIFT 16 |
| 495 | |
| 496 | /* RCC_PLL2CR register fields */ |
| 497 | #define RCC_PLL2CR_PLLON BIT(0) |
| 498 | #define RCC_PLL2CR_PLL2RDY BIT(1) |
| 499 | #define RCC_PLL2CR_SSCG_CTRL BIT(2) |
| 500 | #define RCC_PLL2CR_DIVPEN BIT(4) |
| 501 | #define RCC_PLL2CR_DIVQEN BIT(5) |
| 502 | #define RCC_PLL2CR_DIVREN BIT(6) |
| 503 | |
| 504 | /* RCC_PLL2CFGR1 register fields */ |
| 505 | #define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) |
| 506 | #define RCC_PLL2CFGR1_DIVN_SHIFT 0 |
| 507 | #define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) |
| 508 | #define RCC_PLL2CFGR1_DIVM2_SHIFT 16 |
| 509 | |
| 510 | /* RCC_PLL2CFGR2 register fields */ |
| 511 | #define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) |
| 512 | #define RCC_PLL2CFGR2_DIVP_SHIFT 0 |
| 513 | #define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) |
| 514 | #define RCC_PLL2CFGR2_DIVQ_SHIFT 8 |
| 515 | #define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) |
| 516 | #define RCC_PLL2CFGR2_DIVR_SHIFT 16 |
| 517 | |
| 518 | /* RCC_PLL2FRACR register fields */ |
| 519 | #define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) |
| 520 | #define RCC_PLL2FRACR_FRACV_SHIFT 3 |
| 521 | #define RCC_PLL2FRACR_FRACLE BIT(16) |
| 522 | |
| 523 | /* RCC_PLL2CSGR register fields */ |
| 524 | #define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) |
| 525 | #define RCC_PLL2CSGR_MOD_PER_SHIFT 0 |
| 526 | #define RCC_PLL2CSGR_TPDFN_DIS BIT(13) |
| 527 | #define RCC_PLL2CSGR_RPDFN_DIS BIT(14) |
| 528 | #define RCC_PLL2CSGR_SSCG_MODE BIT(15) |
| 529 | #define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) |
| 530 | #define RCC_PLL2CSGR_INC_STEP_SHIFT 16 |
| 531 | |
| 532 | /* RCC_PLL3CR register fields */ |
| 533 | #define RCC_PLL3CR_PLLON BIT(0) |
| 534 | #define RCC_PLL3CR_PLL3RDY BIT(1) |
| 535 | #define RCC_PLL3CR_SSCG_CTRL BIT(2) |
| 536 | #define RCC_PLL3CR_DIVPEN BIT(4) |
| 537 | #define RCC_PLL3CR_DIVQEN BIT(5) |
| 538 | #define RCC_PLL3CR_DIVREN BIT(6) |
| 539 | |
| 540 | /* RCC_PLL3CFGR1 register fields */ |
| 541 | #define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) |
| 542 | #define RCC_PLL3CFGR1_DIVN_SHIFT 0 |
| 543 | #define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) |
| 544 | #define RCC_PLL3CFGR1_DIVM3_SHIFT 16 |
| 545 | #define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) |
| 546 | #define RCC_PLL3CFGR1_IFRGE_SHIFT 24 |
| 547 | |
| 548 | /* RCC_PLL3CFGR2 register fields */ |
| 549 | #define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) |
| 550 | #define RCC_PLL3CFGR2_DIVP_SHIFT 0 |
| 551 | #define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) |
| 552 | #define RCC_PLL3CFGR2_DIVQ_SHIFT 8 |
| 553 | #define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) |
| 554 | #define RCC_PLL3CFGR2_DIVR_SHIFT 16 |
| 555 | |
| 556 | /* RCC_PLL3FRACR register fields */ |
| 557 | #define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) |
| 558 | #define RCC_PLL3FRACR_FRACV_SHIFT 3 |
| 559 | #define RCC_PLL3FRACR_FRACLE BIT(16) |
| 560 | |
| 561 | /* RCC_PLL3CSGR register fields */ |
| 562 | #define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) |
| 563 | #define RCC_PLL3CSGR_MOD_PER_SHIFT 0 |
| 564 | #define RCC_PLL3CSGR_TPDFN_DIS BIT(13) |
| 565 | #define RCC_PLL3CSGR_RPDFN_DIS BIT(14) |
| 566 | #define RCC_PLL3CSGR_SSCG_MODE BIT(15) |
| 567 | #define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) |
| 568 | #define RCC_PLL3CSGR_INC_STEP_SHIFT 16 |
| 569 | |
| 570 | /* RCC_PLL4CR register fields */ |
| 571 | #define RCC_PLL4CR_PLLON BIT(0) |
| 572 | #define RCC_PLL4CR_PLL4RDY BIT(1) |
| 573 | #define RCC_PLL4CR_SSCG_CTRL BIT(2) |
| 574 | #define RCC_PLL4CR_DIVPEN BIT(4) |
| 575 | #define RCC_PLL4CR_DIVQEN BIT(5) |
| 576 | #define RCC_PLL4CR_DIVREN BIT(6) |
| 577 | |
| 578 | /* RCC_PLL4CFGR1 register fields */ |
| 579 | #define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) |
| 580 | #define RCC_PLL4CFGR1_DIVN_SHIFT 0 |
| 581 | #define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) |
| 582 | #define RCC_PLL4CFGR1_DIVM4_SHIFT 16 |
| 583 | #define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) |
| 584 | #define RCC_PLL4CFGR1_IFRGE_SHIFT 24 |
| 585 | |
| 586 | /* RCC_PLL4CFGR2 register fields */ |
| 587 | #define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) |
| 588 | #define RCC_PLL4CFGR2_DIVP_SHIFT 0 |
| 589 | #define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) |
| 590 | #define RCC_PLL4CFGR2_DIVQ_SHIFT 8 |
| 591 | #define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) |
| 592 | #define RCC_PLL4CFGR2_DIVR_SHIFT 16 |
| 593 | |
| 594 | /* RCC_PLL4FRACR register fields */ |
| 595 | #define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) |
| 596 | #define RCC_PLL4FRACR_FRACV_SHIFT 3 |
| 597 | #define RCC_PLL4FRACR_FRACLE BIT(16) |
| 598 | |
| 599 | /* RCC_PLL4CSGR register fields */ |
| 600 | #define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) |
| 601 | #define RCC_PLL4CSGR_MOD_PER_SHIFT 0 |
| 602 | #define RCC_PLL4CSGR_TPDFN_DIS BIT(13) |
| 603 | #define RCC_PLL4CSGR_RPDFN_DIS BIT(14) |
| 604 | #define RCC_PLL4CSGR_SSCG_MODE BIT(15) |
| 605 | #define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) |
| 606 | #define RCC_PLL4CSGR_INC_STEP_SHIFT 16 |
| 607 | |
| 608 | /* RCC_MPCKSELR register fields */ |
| 609 | #define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) |
| 610 | #define RCC_MPCKSELR_MPUSRC_SHIFT 0 |
| 611 | #define RCC_MPCKSELR_MPUSRCRDY BIT(31) |
| 612 | |
| 613 | /* RCC_ASSCKSELR register fields */ |
| 614 | #define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) |
| 615 | #define RCC_ASSCKSELR_AXISSRC_SHIFT 0 |
| 616 | #define RCC_ASSCKSELR_AXISSRCRDY BIT(31) |
| 617 | |
| 618 | /* RCC_MSSCKSELR register fields */ |
| 619 | #define RCC_MSSCKSELR_MLAHBSSRC_MASK GENMASK(1, 0) |
| 620 | #define RCC_MSSCKSELR_MLAHBSSRC_SHIFT 0 |
| 621 | #define RCC_MSSCKSELR_MLAHBSSRCRDY BIT(31) |
| 622 | |
| 623 | /* RCC_CPERCKSELR register fields */ |
| 624 | #define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) |
| 625 | #define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 |
| 626 | |
| 627 | /* RCC_RTCDIVR register fields */ |
| 628 | #define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) |
| 629 | #define RCC_RTCDIVR_RTCDIV_SHIFT 0 |
| 630 | |
| 631 | /* RCC_MPCKDIVR register fields */ |
| 632 | #define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(3, 0) |
| 633 | #define RCC_MPCKDIVR_MPUDIV_SHIFT 0 |
| 634 | #define RCC_MPCKDIVR_MPUDIVRDY BIT(31) |
| 635 | |
| 636 | /* RCC_AXIDIVR register fields */ |
| 637 | #define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) |
| 638 | #define RCC_AXIDIVR_AXIDIV_SHIFT 0 |
| 639 | #define RCC_AXIDIVR_AXIDIVRDY BIT(31) |
| 640 | |
| 641 | /* RCC_MLAHBDIVR register fields */ |
| 642 | #define RCC_MLAHBDIVR_MLAHBDIV_MASK GENMASK(3, 0) |
| 643 | #define RCC_MLAHBDIVR_MLAHBDIV_SHIFT 0 |
| 644 | #define RCC_MLAHBDIVR_MLAHBDIVRDY BIT(31) |
| 645 | |
| 646 | /* RCC_APB1DIVR register fields */ |
| 647 | #define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) |
| 648 | #define RCC_APB1DIVR_APB1DIV_SHIFT 0 |
| 649 | #define RCC_APB1DIVR_APB1DIVRDY BIT(31) |
| 650 | |
| 651 | /* RCC_APB2DIVR register fields */ |
| 652 | #define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) |
| 653 | #define RCC_APB2DIVR_APB2DIV_SHIFT 0 |
| 654 | #define RCC_APB2DIVR_APB2DIVRDY BIT(31) |
| 655 | |
| 656 | /* RCC_APB3DIVR register fields */ |
| 657 | #define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) |
| 658 | #define RCC_APB3DIVR_APB3DIV_SHIFT 0 |
| 659 | #define RCC_APB3DIVR_APB3DIVRDY BIT(31) |
| 660 | |
| 661 | /* RCC_APB4DIVR register fields */ |
| 662 | #define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) |
| 663 | #define RCC_APB4DIVR_APB4DIV_SHIFT 0 |
| 664 | #define RCC_APB4DIVR_APB4DIVRDY BIT(31) |
| 665 | |
| 666 | /* RCC_APB5DIVR register fields */ |
| 667 | #define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) |
| 668 | #define RCC_APB5DIVR_APB5DIV_SHIFT 0 |
| 669 | #define RCC_APB5DIVR_APB5DIVRDY BIT(31) |
| 670 | |
| 671 | /* RCC_APB6DIVR register fields */ |
| 672 | #define RCC_APB6DIVR_APB6DIV_MASK GENMASK(2, 0) |
| 673 | #define RCC_APB6DIVR_APB6DIV_SHIFT 0 |
| 674 | #define RCC_APB6DIVR_APB6DIVRDY BIT(31) |
| 675 | |
| 676 | /* RCC_TIMG1PRER register fields */ |
| 677 | #define RCC_TIMG1PRER_TIMG1PRE BIT(0) |
| 678 | #define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) |
| 679 | |
| 680 | /* RCC_TIMG2PRER register fields */ |
| 681 | #define RCC_TIMG2PRER_TIMG2PRE BIT(0) |
| 682 | #define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) |
| 683 | |
| 684 | /* RCC_TIMG3PRER register fields */ |
| 685 | #define RCC_TIMG3PRER_TIMG3PRE BIT(0) |
| 686 | #define RCC_TIMG3PRER_TIMG3PRERDY BIT(31) |
| 687 | |
| 688 | /* RCC_DDRITFCR register fields */ |
| 689 | #define RCC_DDRITFCR_DDRC1EN BIT(0) |
| 690 | #define RCC_DDRITFCR_DDRC1LPEN BIT(1) |
| 691 | #define RCC_DDRITFCR_DDRPHYCEN BIT(4) |
| 692 | #define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) |
| 693 | #define RCC_DDRITFCR_DDRCAPBEN BIT(6) |
| 694 | #define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) |
| 695 | #define RCC_DDRITFCR_AXIDCGEN BIT(8) |
| 696 | #define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) |
| 697 | #define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) |
| 698 | #define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) |
| 699 | #define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 |
| 700 | #define RCC_DDRITFCR_DDRCAPBRST BIT(14) |
| 701 | #define RCC_DDRITFCR_DDRCAXIRST BIT(15) |
| 702 | #define RCC_DDRITFCR_DDRCORERST BIT(16) |
| 703 | #define RCC_DDRITFCR_DPHYAPBRST BIT(17) |
| 704 | #define RCC_DDRITFCR_DPHYRST BIT(18) |
| 705 | #define RCC_DDRITFCR_DPHYCTLRST BIT(19) |
| 706 | #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) |
| 707 | #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 |
| 708 | #define RCC_DDRITFCR_GSKPMOD BIT(23) |
| 709 | #define RCC_DDRITFCR_GSKPCTRL BIT(24) |
| 710 | #define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) |
| 711 | #define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 |
| 712 | #define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) |
| 713 | #define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 |
| 714 | |
| 715 | /* RCC_I2C12CKSELR register fields */ |
| 716 | #define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) |
| 717 | #define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 |
| 718 | |
| 719 | /* RCC_I2C345CKSELR register fields */ |
| 720 | #define RCC_I2C345CKSELR_I2C3SRC_MASK GENMASK(2, 0) |
| 721 | #define RCC_I2C345CKSELR_I2C3SRC_SHIFT 0 |
| 722 | #define RCC_I2C345CKSELR_I2C4SRC_MASK GENMASK(5, 3) |
| 723 | #define RCC_I2C345CKSELR_I2C4SRC_SHIFT 3 |
| 724 | #define RCC_I2C345CKSELR_I2C5SRC_MASK GENMASK(8, 6) |
| 725 | #define RCC_I2C345CKSELR_I2C5SRC_SHIFT 6 |
| 726 | |
| 727 | /* RCC_SPI2S1CKSELR register fields */ |
| 728 | #define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) |
| 729 | #define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 |
| 730 | |
| 731 | /* RCC_SPI2S23CKSELR register fields */ |
| 732 | #define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) |
| 733 | #define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 |
| 734 | |
| 735 | /* RCC_SPI45CKSELR register fields */ |
| 736 | #define RCC_SPI45CKSELR_SPI4SRC_MASK GENMASK(2, 0) |
| 737 | #define RCC_SPI45CKSELR_SPI4SRC_SHIFT 0 |
| 738 | #define RCC_SPI45CKSELR_SPI5SRC_MASK GENMASK(5, 3) |
| 739 | #define RCC_SPI45CKSELR_SPI5SRC_SHIFT 3 |
| 740 | |
| 741 | /* RCC_UART12CKSELR register fields */ |
| 742 | #define RCC_UART12CKSELR_UART1SRC_MASK GENMASK(2, 0) |
| 743 | #define RCC_UART12CKSELR_UART1SRC_SHIFT 0 |
| 744 | #define RCC_UART12CKSELR_UART2SRC_MASK GENMASK(5, 3) |
| 745 | #define RCC_UART12CKSELR_UART2SRC_SHIFT 3 |
| 746 | |
| 747 | /* RCC_UART35CKSELR register fields */ |
| 748 | #define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) |
| 749 | #define RCC_UART35CKSELR_UART35SRC_SHIFT 0 |
| 750 | |
| 751 | /* RCC_UART4CKSELR register fields */ |
| 752 | #define RCC_UART4CKSELR_UART4SRC_MASK GENMASK(2, 0) |
| 753 | #define RCC_UART4CKSELR_UART4SRC_SHIFT 0 |
| 754 | |
| 755 | /* RCC_UART6CKSELR register fields */ |
| 756 | #define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) |
| 757 | #define RCC_UART6CKSELR_UART6SRC_SHIFT 0 |
| 758 | |
| 759 | /* RCC_UART78CKSELR register fields */ |
| 760 | #define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) |
| 761 | #define RCC_UART78CKSELR_UART78SRC_SHIFT 0 |
| 762 | |
| 763 | /* RCC_LPTIM1CKSELR register fields */ |
| 764 | #define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) |
| 765 | #define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 |
| 766 | |
| 767 | /* RCC_LPTIM23CKSELR register fields */ |
| 768 | #define RCC_LPTIM23CKSELR_LPTIM2SRC_MASK GENMASK(2, 0) |
| 769 | #define RCC_LPTIM23CKSELR_LPTIM2SRC_SHIFT 0 |
| 770 | #define RCC_LPTIM23CKSELR_LPTIM3SRC_MASK GENMASK(5, 3) |
| 771 | #define RCC_LPTIM23CKSELR_LPTIM3SRC_SHIFT 3 |
| 772 | |
| 773 | /* RCC_LPTIM45CKSELR register fields */ |
| 774 | #define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) |
| 775 | #define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 |
| 776 | |
| 777 | /* RCC_SAI1CKSELR register fields */ |
| 778 | #define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) |
| 779 | #define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 |
| 780 | |
| 781 | /* RCC_SAI2CKSELR register fields */ |
| 782 | #define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) |
| 783 | #define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 |
| 784 | |
| 785 | /* RCC_FDCANCKSELR register fields */ |
| 786 | #define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) |
| 787 | #define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 |
| 788 | |
| 789 | /* RCC_SPDIFCKSELR register fields */ |
| 790 | #define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) |
| 791 | #define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 |
| 792 | |
| 793 | /* RCC_ADC12CKSELR register fields */ |
| 794 | #define RCC_ADC12CKSELR_ADC1SRC_MASK GENMASK(1, 0) |
| 795 | #define RCC_ADC12CKSELR_ADC1SRC_SHIFT 0 |
| 796 | #define RCC_ADC12CKSELR_ADC2SRC_MASK GENMASK(3, 2) |
| 797 | #define RCC_ADC12CKSELR_ADC2SRC_SHIFT 2 |
| 798 | |
| 799 | /* RCC_SDMMC12CKSELR register fields */ |
| 800 | #define RCC_SDMMC12CKSELR_SDMMC1SRC_MASK GENMASK(2, 0) |
| 801 | #define RCC_SDMMC12CKSELR_SDMMC1SRC_SHIFT 0 |
| 802 | #define RCC_SDMMC12CKSELR_SDMMC2SRC_MASK GENMASK(5, 3) |
| 803 | #define RCC_SDMMC12CKSELR_SDMMC2SRC_SHIFT 3 |
| 804 | |
| 805 | /* RCC_ETH12CKSELR register fields */ |
| 806 | #define RCC_ETH12CKSELR_ETH1SRC_MASK GENMASK(1, 0) |
| 807 | #define RCC_ETH12CKSELR_ETH1SRC_SHIFT 0 |
| 808 | #define RCC_ETH12CKSELR_ETH1PTPDIV_MASK GENMASK(7, 4) |
| 809 | #define RCC_ETH12CKSELR_ETH1PTPDIV_SHIFT 4 |
| 810 | #define RCC_ETH12CKSELR_ETH2SRC_MASK GENMASK(9, 8) |
| 811 | #define RCC_ETH12CKSELR_ETH2SRC_SHIFT 8 |
| 812 | #define RCC_ETH12CKSELR_ETH2PTPDIV_MASK GENMASK(15, 12) |
| 813 | #define RCC_ETH12CKSELR_ETH2PTPDIV_SHIFT 12 |
| 814 | |
| 815 | /* RCC_USBCKSELR register fields */ |
| 816 | #define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) |
| 817 | #define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 |
| 818 | #define RCC_USBCKSELR_USBOSRC BIT(4) |
| 819 | |
| 820 | /* RCC_QSPICKSELR register fields */ |
| 821 | #define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) |
| 822 | #define RCC_QSPICKSELR_QSPISRC_SHIFT 0 |
| 823 | |
| 824 | /* RCC_FMCCKSELR register fields */ |
| 825 | #define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) |
| 826 | #define RCC_FMCCKSELR_FMCSRC_SHIFT 0 |
| 827 | |
| 828 | /* RCC_RNG1CKSELR register fields */ |
| 829 | #define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) |
| 830 | #define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 |
| 831 | |
| 832 | /* RCC_STGENCKSELR register fields */ |
| 833 | #define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) |
| 834 | #define RCC_STGENCKSELR_STGENSRC_SHIFT 0 |
| 835 | |
| 836 | /* RCC_DCMIPPCKSELR register fields */ |
| 837 | #define RCC_DCMIPPCKSELR_DCMIPPSRC_MASK GENMASK(1, 0) |
| 838 | #define RCC_DCMIPPCKSELR_DCMIPPSRC_SHIFT 0 |
| 839 | |
| 840 | /* RCC_SAESCKSELR register fields */ |
| 841 | #define RCC_SAESCKSELR_SAESSRC_MASK GENMASK(1, 0) |
| 842 | #define RCC_SAESCKSELR_SAESSRC_SHIFT 0 |
| 843 | |
| 844 | /* RCC_APB1RSTSETR register fields */ |
| 845 | #define RCC_APB1RSTSETR_TIM2RST BIT(0) |
| 846 | #define RCC_APB1RSTSETR_TIM3RST BIT(1) |
| 847 | #define RCC_APB1RSTSETR_TIM4RST BIT(2) |
| 848 | #define RCC_APB1RSTSETR_TIM5RST BIT(3) |
| 849 | #define RCC_APB1RSTSETR_TIM6RST BIT(4) |
| 850 | #define RCC_APB1RSTSETR_TIM7RST BIT(5) |
| 851 | #define RCC_APB1RSTSETR_LPTIM1RST BIT(9) |
| 852 | #define RCC_APB1RSTSETR_SPI2RST BIT(11) |
| 853 | #define RCC_APB1RSTSETR_SPI3RST BIT(12) |
| 854 | #define RCC_APB1RSTSETR_USART3RST BIT(15) |
| 855 | #define RCC_APB1RSTSETR_UART4RST BIT(16) |
| 856 | #define RCC_APB1RSTSETR_UART5RST BIT(17) |
| 857 | #define RCC_APB1RSTSETR_UART7RST BIT(18) |
| 858 | #define RCC_APB1RSTSETR_UART8RST BIT(19) |
| 859 | #define RCC_APB1RSTSETR_I2C1RST BIT(21) |
| 860 | #define RCC_APB1RSTSETR_I2C2RST BIT(22) |
| 861 | #define RCC_APB1RSTSETR_SPDIFRST BIT(26) |
| 862 | |
| 863 | /* RCC_APB1RSTCLRR register fields */ |
| 864 | #define RCC_APB1RSTCLRR_TIM2RST BIT(0) |
| 865 | #define RCC_APB1RSTCLRR_TIM3RST BIT(1) |
| 866 | #define RCC_APB1RSTCLRR_TIM4RST BIT(2) |
| 867 | #define RCC_APB1RSTCLRR_TIM5RST BIT(3) |
| 868 | #define RCC_APB1RSTCLRR_TIM6RST BIT(4) |
| 869 | #define RCC_APB1RSTCLRR_TIM7RST BIT(5) |
| 870 | #define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) |
| 871 | #define RCC_APB1RSTCLRR_SPI2RST BIT(11) |
| 872 | #define RCC_APB1RSTCLRR_SPI3RST BIT(12) |
| 873 | #define RCC_APB1RSTCLRR_USART3RST BIT(15) |
| 874 | #define RCC_APB1RSTCLRR_UART4RST BIT(16) |
| 875 | #define RCC_APB1RSTCLRR_UART5RST BIT(17) |
| 876 | #define RCC_APB1RSTCLRR_UART7RST BIT(18) |
| 877 | #define RCC_APB1RSTCLRR_UART8RST BIT(19) |
| 878 | #define RCC_APB1RSTCLRR_I2C1RST BIT(21) |
| 879 | #define RCC_APB1RSTCLRR_I2C2RST BIT(22) |
| 880 | #define RCC_APB1RSTCLRR_SPDIFRST BIT(26) |
| 881 | |
| 882 | /* RCC_APB2RSTSETR register fields */ |
| 883 | #define RCC_APB2RSTSETR_TIM1RST BIT(0) |
| 884 | #define RCC_APB2RSTSETR_TIM8RST BIT(1) |
| 885 | #define RCC_APB2RSTSETR_SPI1RST BIT(8) |
| 886 | #define RCC_APB2RSTSETR_USART6RST BIT(13) |
| 887 | #define RCC_APB2RSTSETR_SAI1RST BIT(16) |
| 888 | #define RCC_APB2RSTSETR_SAI2RST BIT(17) |
| 889 | #define RCC_APB2RSTSETR_DFSDMRST BIT(20) |
| 890 | #define RCC_APB2RSTSETR_FDCANRST BIT(24) |
| 891 | |
| 892 | /* RCC_APB2RSTCLRR register fields */ |
| 893 | #define RCC_APB2RSTCLRR_TIM1RST BIT(0) |
| 894 | #define RCC_APB2RSTCLRR_TIM8RST BIT(1) |
| 895 | #define RCC_APB2RSTCLRR_SPI1RST BIT(8) |
| 896 | #define RCC_APB2RSTCLRR_USART6RST BIT(13) |
| 897 | #define RCC_APB2RSTCLRR_SAI1RST BIT(16) |
| 898 | #define RCC_APB2RSTCLRR_SAI2RST BIT(17) |
| 899 | #define RCC_APB2RSTCLRR_DFSDMRST BIT(20) |
| 900 | #define RCC_APB2RSTCLRR_FDCANRST BIT(24) |
| 901 | |
| 902 | /* RCC_APB3RSTSETR register fields */ |
| 903 | #define RCC_APB3RSTSETR_LPTIM2RST BIT(0) |
| 904 | #define RCC_APB3RSTSETR_LPTIM3RST BIT(1) |
| 905 | #define RCC_APB3RSTSETR_LPTIM4RST BIT(2) |
| 906 | #define RCC_APB3RSTSETR_LPTIM5RST BIT(3) |
| 907 | #define RCC_APB3RSTSETR_SYSCFGRST BIT(11) |
| 908 | #define RCC_APB3RSTSETR_VREFRST BIT(13) |
| 909 | #define RCC_APB3RSTSETR_DTSRST BIT(16) |
| 910 | #define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) |
| 911 | |
| 912 | /* RCC_APB3RSTCLRR register fields */ |
| 913 | #define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) |
| 914 | #define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) |
| 915 | #define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) |
| 916 | #define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) |
| 917 | #define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) |
| 918 | #define RCC_APB3RSTCLRR_VREFRST BIT(13) |
| 919 | #define RCC_APB3RSTCLRR_DTSRST BIT(16) |
| 920 | #define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) |
| 921 | |
| 922 | /* RCC_APB4RSTSETR register fields */ |
| 923 | #define RCC_APB4RSTSETR_LTDCRST BIT(0) |
| 924 | #define RCC_APB4RSTSETR_DCMIPPRST BIT(1) |
| 925 | #define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) |
| 926 | #define RCC_APB4RSTSETR_USBPHYRST BIT(16) |
| 927 | |
| 928 | /* RCC_APB4RSTCLRR register fields */ |
| 929 | #define RCC_APB4RSTCLRR_LTDCRST BIT(0) |
| 930 | #define RCC_APB4RSTCLRR_DCMIPPRST BIT(1) |
| 931 | #define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) |
| 932 | #define RCC_APB4RSTCLRR_USBPHYRST BIT(16) |
| 933 | |
| 934 | /* RCC_APB5RSTSETR register fields */ |
| 935 | #define RCC_APB5RSTSETR_STGENRST BIT(20) |
| 936 | |
| 937 | /* RCC_APB5RSTCLRR register fields */ |
| 938 | #define RCC_APB5RSTCLRR_STGENRST BIT(20) |
| 939 | |
| 940 | /* RCC_APB6RSTSETR register fields */ |
| 941 | #define RCC_APB6RSTSETR_USART1RST BIT(0) |
| 942 | #define RCC_APB6RSTSETR_USART2RST BIT(1) |
| 943 | #define RCC_APB6RSTSETR_SPI4RST BIT(2) |
| 944 | #define RCC_APB6RSTSETR_SPI5RST BIT(3) |
| 945 | #define RCC_APB6RSTSETR_I2C3RST BIT(4) |
| 946 | #define RCC_APB6RSTSETR_I2C4RST BIT(5) |
| 947 | #define RCC_APB6RSTSETR_I2C5RST BIT(6) |
| 948 | #define RCC_APB6RSTSETR_TIM12RST BIT(7) |
| 949 | #define RCC_APB6RSTSETR_TIM13RST BIT(8) |
| 950 | #define RCC_APB6RSTSETR_TIM14RST BIT(9) |
| 951 | #define RCC_APB6RSTSETR_TIM15RST BIT(10) |
| 952 | #define RCC_APB6RSTSETR_TIM16RST BIT(11) |
| 953 | #define RCC_APB6RSTSETR_TIM17RST BIT(12) |
| 954 | |
| 955 | /* RCC_APB6RSTCLRR register fields */ |
| 956 | #define RCC_APB6RSTCLRR_USART1RST BIT(0) |
| 957 | #define RCC_APB6RSTCLRR_USART2RST BIT(1) |
| 958 | #define RCC_APB6RSTCLRR_SPI4RST BIT(2) |
| 959 | #define RCC_APB6RSTCLRR_SPI5RST BIT(3) |
| 960 | #define RCC_APB6RSTCLRR_I2C3RST BIT(4) |
| 961 | #define RCC_APB6RSTCLRR_I2C4RST BIT(5) |
| 962 | #define RCC_APB6RSTCLRR_I2C5RST BIT(6) |
| 963 | #define RCC_APB6RSTCLRR_TIM12RST BIT(7) |
| 964 | #define RCC_APB6RSTCLRR_TIM13RST BIT(8) |
| 965 | #define RCC_APB6RSTCLRR_TIM14RST BIT(9) |
| 966 | #define RCC_APB6RSTCLRR_TIM15RST BIT(10) |
| 967 | #define RCC_APB6RSTCLRR_TIM16RST BIT(11) |
| 968 | #define RCC_APB6RSTCLRR_TIM17RST BIT(12) |
| 969 | |
| 970 | /* RCC_AHB2RSTSETR register fields */ |
| 971 | #define RCC_AHB2RSTSETR_DMA1RST BIT(0) |
| 972 | #define RCC_AHB2RSTSETR_DMA2RST BIT(1) |
| 973 | #define RCC_AHB2RSTSETR_DMAMUX1RST BIT(2) |
| 974 | #define RCC_AHB2RSTSETR_DMA3RST BIT(3) |
| 975 | #define RCC_AHB2RSTSETR_DMAMUX2RST BIT(4) |
| 976 | #define RCC_AHB2RSTSETR_ADC1RST BIT(5) |
| 977 | #define RCC_AHB2RSTSETR_ADC2RST BIT(6) |
| 978 | #define RCC_AHB2RSTSETR_USBORST BIT(8) |
| 979 | |
| 980 | /* RCC_AHB2RSTCLRR register fields */ |
| 981 | #define RCC_AHB2RSTCLRR_DMA1RST BIT(0) |
| 982 | #define RCC_AHB2RSTCLRR_DMA2RST BIT(1) |
| 983 | #define RCC_AHB2RSTCLRR_DMAMUX1RST BIT(2) |
| 984 | #define RCC_AHB2RSTCLRR_DMA3RST BIT(3) |
| 985 | #define RCC_AHB2RSTCLRR_DMAMUX2RST BIT(4) |
| 986 | #define RCC_AHB2RSTCLRR_ADC1RST BIT(5) |
| 987 | #define RCC_AHB2RSTCLRR_ADC2RST BIT(6) |
| 988 | #define RCC_AHB2RSTCLRR_USBORST BIT(8) |
| 989 | |
| 990 | /* RCC_AHB4RSTSETR register fields */ |
| 991 | #define RCC_AHB4RSTSETR_GPIOARST BIT(0) |
| 992 | #define RCC_AHB4RSTSETR_GPIOBRST BIT(1) |
| 993 | #define RCC_AHB4RSTSETR_GPIOCRST BIT(2) |
| 994 | #define RCC_AHB4RSTSETR_GPIODRST BIT(3) |
| 995 | #define RCC_AHB4RSTSETR_GPIOERST BIT(4) |
| 996 | #define RCC_AHB4RSTSETR_GPIOFRST BIT(5) |
| 997 | #define RCC_AHB4RSTSETR_GPIOGRST BIT(6) |
| 998 | #define RCC_AHB4RSTSETR_GPIOHRST BIT(7) |
| 999 | #define RCC_AHB4RSTSETR_GPIOIRST BIT(8) |
| 1000 | #define RCC_AHB4RSTSETR_TSCRST BIT(15) |
| 1001 | |
| 1002 | /* RCC_AHB4RSTCLRR register fields */ |
| 1003 | #define RCC_AHB4RSTCLRR_GPIOARST BIT(0) |
| 1004 | #define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) |
| 1005 | #define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) |
| 1006 | #define RCC_AHB4RSTCLRR_GPIODRST BIT(3) |
| 1007 | #define RCC_AHB4RSTCLRR_GPIOERST BIT(4) |
| 1008 | #define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) |
| 1009 | #define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) |
| 1010 | #define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) |
| 1011 | #define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) |
| 1012 | #define RCC_AHB4RSTCLRR_TSCRST BIT(15) |
| 1013 | |
| 1014 | /* RCC_AHB5RSTSETR register fields */ |
| 1015 | #define RCC_AHB5RSTSETR_PKARST BIT(2) |
| 1016 | #define RCC_AHB5RSTSETR_SAESRST BIT(3) |
| 1017 | #define RCC_AHB5RSTSETR_CRYP1RST BIT(4) |
| 1018 | #define RCC_AHB5RSTSETR_HASH1RST BIT(5) |
| 1019 | #define RCC_AHB5RSTSETR_RNG1RST BIT(6) |
| 1020 | #define RCC_AHB5RSTSETR_AXIMCRST BIT(16) |
| 1021 | |
| 1022 | /* RCC_AHB5RSTCLRR register fields */ |
| 1023 | #define RCC_AHB5RSTCLRR_PKARST BIT(2) |
| 1024 | #define RCC_AHB5RSTCLRR_SAESRST BIT(3) |
| 1025 | #define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) |
| 1026 | #define RCC_AHB5RSTCLRR_HASH1RST BIT(5) |
| 1027 | #define RCC_AHB5RSTCLRR_RNG1RST BIT(6) |
| 1028 | #define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) |
| 1029 | |
| 1030 | /* RCC_AHB6RSTSETR register fields */ |
| 1031 | #define RCC_AHB6RSTSETR_MDMARST BIT(0) |
| 1032 | #define RCC_AHB6RSTSETR_MCERST BIT(1) |
| 1033 | #define RCC_AHB6RSTSETR_ETH1MACRST BIT(10) |
| 1034 | #define RCC_AHB6RSTSETR_FMCRST BIT(12) |
| 1035 | #define RCC_AHB6RSTSETR_QSPIRST BIT(14) |
| 1036 | #define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) |
| 1037 | #define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) |
| 1038 | #define RCC_AHB6RSTSETR_CRC1RST BIT(20) |
| 1039 | #define RCC_AHB6RSTSETR_USBHRST BIT(24) |
| 1040 | #define RCC_AHB6RSTSETR_ETH2MACRST BIT(30) |
| 1041 | |
| 1042 | /* RCC_AHB6RSTCLRR register fields */ |
| 1043 | #define RCC_AHB6RSTCLRR_MDMARST BIT(0) |
| 1044 | #define RCC_AHB6RSTCLRR_MCERST BIT(1) |
| 1045 | #define RCC_AHB6RSTCLRR_ETH1MACRST BIT(10) |
| 1046 | #define RCC_AHB6RSTCLRR_FMCRST BIT(12) |
| 1047 | #define RCC_AHB6RSTCLRR_QSPIRST BIT(14) |
| 1048 | #define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) |
| 1049 | #define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) |
| 1050 | #define RCC_AHB6RSTCLRR_CRC1RST BIT(20) |
| 1051 | #define RCC_AHB6RSTCLRR_USBHRST BIT(24) |
| 1052 | #define RCC_AHB6RSTCLRR_ETH2MACRST BIT(30) |
| 1053 | |
| 1054 | /* RCC_MP_APB1ENSETR register fields */ |
| 1055 | #define RCC_MP_APB1ENSETR_TIM2EN BIT(0) |
| 1056 | #define RCC_MP_APB1ENSETR_TIM3EN BIT(1) |
| 1057 | #define RCC_MP_APB1ENSETR_TIM4EN BIT(2) |
| 1058 | #define RCC_MP_APB1ENSETR_TIM5EN BIT(3) |
| 1059 | #define RCC_MP_APB1ENSETR_TIM6EN BIT(4) |
| 1060 | #define RCC_MP_APB1ENSETR_TIM7EN BIT(5) |
| 1061 | #define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) |
| 1062 | #define RCC_MP_APB1ENSETR_SPI2EN BIT(11) |
| 1063 | #define RCC_MP_APB1ENSETR_SPI3EN BIT(12) |
| 1064 | #define RCC_MP_APB1ENSETR_USART3EN BIT(15) |
| 1065 | #define RCC_MP_APB1ENSETR_UART4EN BIT(16) |
| 1066 | #define RCC_MP_APB1ENSETR_UART5EN BIT(17) |
| 1067 | #define RCC_MP_APB1ENSETR_UART7EN BIT(18) |
| 1068 | #define RCC_MP_APB1ENSETR_UART8EN BIT(19) |
| 1069 | #define RCC_MP_APB1ENSETR_I2C1EN BIT(21) |
| 1070 | #define RCC_MP_APB1ENSETR_I2C2EN BIT(22) |
| 1071 | #define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) |
| 1072 | |
| 1073 | /* RCC_MP_APB1ENCLRR register fields */ |
| 1074 | #define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) |
| 1075 | #define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) |
| 1076 | #define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) |
| 1077 | #define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) |
| 1078 | #define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) |
| 1079 | #define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) |
| 1080 | #define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) |
| 1081 | #define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) |
| 1082 | #define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) |
| 1083 | #define RCC_MP_APB1ENCLRR_USART3EN BIT(15) |
| 1084 | #define RCC_MP_APB1ENCLRR_UART4EN BIT(16) |
| 1085 | #define RCC_MP_APB1ENCLRR_UART5EN BIT(17) |
| 1086 | #define RCC_MP_APB1ENCLRR_UART7EN BIT(18) |
| 1087 | #define RCC_MP_APB1ENCLRR_UART8EN BIT(19) |
| 1088 | #define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) |
| 1089 | #define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) |
| 1090 | #define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) |
| 1091 | |
| 1092 | /* RCC_MP_APB2ENSETR register fields */ |
| 1093 | #define RCC_MP_APB2ENSETR_TIM1EN BIT(0) |
| 1094 | #define RCC_MP_APB2ENSETR_TIM8EN BIT(1) |
| 1095 | #define RCC_MP_APB2ENSETR_SPI1EN BIT(8) |
| 1096 | #define RCC_MP_APB2ENSETR_USART6EN BIT(13) |
| 1097 | #define RCC_MP_APB2ENSETR_SAI1EN BIT(16) |
| 1098 | #define RCC_MP_APB2ENSETR_SAI2EN BIT(17) |
| 1099 | #define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) |
| 1100 | #define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) |
| 1101 | #define RCC_MP_APB2ENSETR_FDCANEN BIT(24) |
| 1102 | |
| 1103 | /* RCC_MP_APB2ENCLRR register fields */ |
| 1104 | #define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) |
| 1105 | #define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) |
| 1106 | #define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) |
| 1107 | #define RCC_MP_APB2ENCLRR_USART6EN BIT(13) |
| 1108 | #define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) |
| 1109 | #define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) |
| 1110 | #define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) |
| 1111 | #define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) |
| 1112 | #define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) |
| 1113 | |
| 1114 | /* RCC_MP_APB3ENSETR register fields */ |
| 1115 | #define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) |
| 1116 | #define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) |
| 1117 | #define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) |
| 1118 | #define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) |
| 1119 | #define RCC_MP_APB3ENSETR_VREFEN BIT(13) |
| 1120 | #define RCC_MP_APB3ENSETR_DTSEN BIT(16) |
| 1121 | #define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) |
| 1122 | #define RCC_MP_APB3ENSETR_HDPEN BIT(20) |
| 1123 | |
| 1124 | /* RCC_MP_APB3ENCLRR register fields */ |
| 1125 | #define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) |
| 1126 | #define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) |
| 1127 | #define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) |
| 1128 | #define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) |
| 1129 | #define RCC_MP_APB3ENCLRR_VREFEN BIT(13) |
| 1130 | #define RCC_MP_APB3ENCLRR_DTSEN BIT(16) |
| 1131 | #define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) |
| 1132 | #define RCC_MP_APB3ENCLRR_HDPEN BIT(20) |
| 1133 | |
| 1134 | /* RCC_MP_S_APB3ENSETR register fields */ |
| 1135 | #define RCC_MP_S_APB3ENSETR_SYSCFGEN BIT(0) |
| 1136 | |
| 1137 | /* RCC_MP_S_APB3ENCLRR register fields */ |
| 1138 | #define RCC_MP_S_APB3ENCLRR_SYSCFGEN BIT(0) |
| 1139 | |
| 1140 | /* RCC_MP_NS_APB3ENSETR register fields */ |
| 1141 | #define RCC_MP_NS_APB3ENSETR_SYSCFGEN BIT(0) |
| 1142 | |
| 1143 | /* RCC_MP_NS_APB3ENCLRR register fields */ |
| 1144 | #define RCC_MP_NS_APB3ENCLRR_SYSCFGEN BIT(0) |
| 1145 | |
| 1146 | /* RCC_MP_APB4ENSETR register fields */ |
| 1147 | #define RCC_MP_APB4ENSETR_DCMIPPEN BIT(1) |
| 1148 | #define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) |
| 1149 | #define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) |
| 1150 | #define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) |
| 1151 | #define RCC_MP_APB4ENSETR_STGENROEN BIT(20) |
| 1152 | |
| 1153 | /* RCC_MP_APB4ENCLRR register fields */ |
| 1154 | #define RCC_MP_APB4ENCLRR_DCMIPPEN BIT(1) |
| 1155 | #define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) |
| 1156 | #define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) |
| 1157 | #define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) |
| 1158 | #define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) |
| 1159 | |
| 1160 | /* RCC_MP_S_APB4ENSETR register fields */ |
| 1161 | #define RCC_MP_S_APB4ENSETR_LTDCEN BIT(0) |
| 1162 | |
| 1163 | /* RCC_MP_S_APB4ENCLRR register fields */ |
| 1164 | #define RCC_MP_S_APB4ENCLRR_LTDCEN BIT(0) |
| 1165 | |
| 1166 | /* RCC_MP_NS_APB4ENSETR register fields */ |
| 1167 | #define RCC_MP_NS_APB4ENSETR_LTDCEN BIT(0) |
| 1168 | |
| 1169 | /* RCC_MP_NS_APB4ENCLRR register fields */ |
| 1170 | #define RCC_MP_NS_APB4ENCLRR_LTDCEN BIT(0) |
| 1171 | |
| 1172 | /* RCC_MP_APB5ENSETR register fields */ |
| 1173 | #define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) |
| 1174 | #define RCC_MP_APB5ENSETR_TZCEN BIT(11) |
| 1175 | #define RCC_MP_APB5ENSETR_ETZPCEN BIT(13) |
| 1176 | #define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) |
| 1177 | #define RCC_MP_APB5ENSETR_BSECEN BIT(16) |
| 1178 | #define RCC_MP_APB5ENSETR_STGENCEN BIT(20) |
| 1179 | |
| 1180 | /* RCC_MP_APB5ENCLRR register fields */ |
| 1181 | #define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) |
| 1182 | #define RCC_MP_APB5ENCLRR_TZCEN BIT(11) |
| 1183 | #define RCC_MP_APB5ENCLRR_ETZPCEN BIT(13) |
| 1184 | #define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) |
| 1185 | #define RCC_MP_APB5ENCLRR_BSECEN BIT(16) |
| 1186 | #define RCC_MP_APB5ENCLRR_STGENCEN BIT(20) |
| 1187 | |
| 1188 | /* RCC_MP_APB6ENSETR register fields */ |
| 1189 | #define RCC_MP_APB6ENSETR_USART1EN BIT(0) |
| 1190 | #define RCC_MP_APB6ENSETR_USART2EN BIT(1) |
| 1191 | #define RCC_MP_APB6ENSETR_SPI4EN BIT(2) |
| 1192 | #define RCC_MP_APB6ENSETR_SPI5EN BIT(3) |
| 1193 | #define RCC_MP_APB6ENSETR_I2C3EN BIT(4) |
| 1194 | #define RCC_MP_APB6ENSETR_I2C4EN BIT(5) |
| 1195 | #define RCC_MP_APB6ENSETR_I2C5EN BIT(6) |
| 1196 | #define RCC_MP_APB6ENSETR_TIM12EN BIT(7) |
| 1197 | #define RCC_MP_APB6ENSETR_TIM13EN BIT(8) |
| 1198 | #define RCC_MP_APB6ENSETR_TIM14EN BIT(9) |
| 1199 | #define RCC_MP_APB6ENSETR_TIM15EN BIT(10) |
| 1200 | #define RCC_MP_APB6ENSETR_TIM16EN BIT(11) |
| 1201 | #define RCC_MP_APB6ENSETR_TIM17EN BIT(12) |
| 1202 | |
| 1203 | /* RCC_MP_APB6ENCLRR register fields */ |
| 1204 | #define RCC_MP_APB6ENCLRR_USART1EN BIT(0) |
| 1205 | #define RCC_MP_APB6ENCLRR_USART2EN BIT(1) |
| 1206 | #define RCC_MP_APB6ENCLRR_SPI4EN BIT(2) |
| 1207 | #define RCC_MP_APB6ENCLRR_SPI5EN BIT(3) |
| 1208 | #define RCC_MP_APB6ENCLRR_I2C3EN BIT(4) |
| 1209 | #define RCC_MP_APB6ENCLRR_I2C4EN BIT(5) |
| 1210 | #define RCC_MP_APB6ENCLRR_I2C5EN BIT(6) |
| 1211 | #define RCC_MP_APB6ENCLRR_TIM12EN BIT(7) |
| 1212 | #define RCC_MP_APB6ENCLRR_TIM13EN BIT(8) |
| 1213 | #define RCC_MP_APB6ENCLRR_TIM14EN BIT(9) |
| 1214 | #define RCC_MP_APB6ENCLRR_TIM15EN BIT(10) |
| 1215 | #define RCC_MP_APB6ENCLRR_TIM16EN BIT(11) |
| 1216 | #define RCC_MP_APB6ENCLRR_TIM17EN BIT(12) |
| 1217 | |
| 1218 | /* RCC_MP_AHB2ENSETR register fields */ |
| 1219 | #define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) |
| 1220 | #define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) |
| 1221 | #define RCC_MP_AHB2ENSETR_DMAMUX1EN BIT(2) |
| 1222 | #define RCC_MP_AHB2ENSETR_DMA3EN BIT(3) |
| 1223 | #define RCC_MP_AHB2ENSETR_DMAMUX2EN BIT(4) |
| 1224 | #define RCC_MP_AHB2ENSETR_ADC1EN BIT(5) |
| 1225 | #define RCC_MP_AHB2ENSETR_ADC2EN BIT(6) |
| 1226 | #define RCC_MP_AHB2ENSETR_USBOEN BIT(8) |
| 1227 | |
| 1228 | /* RCC_MP_AHB2ENCLRR register fields */ |
| 1229 | #define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) |
| 1230 | #define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) |
| 1231 | #define RCC_MP_AHB2ENCLRR_DMAMUX1EN BIT(2) |
| 1232 | #define RCC_MP_AHB2ENCLRR_DMA3EN BIT(3) |
| 1233 | #define RCC_MP_AHB2ENCLRR_DMAMUX2EN BIT(4) |
| 1234 | #define RCC_MP_AHB2ENCLRR_ADC1EN BIT(5) |
| 1235 | #define RCC_MP_AHB2ENCLRR_ADC2EN BIT(6) |
| 1236 | #define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) |
| 1237 | |
| 1238 | /* RCC_MP_AHB4ENSETR register fields */ |
| 1239 | #define RCC_MP_AHB4ENSETR_TSCEN BIT(15) |
| 1240 | |
| 1241 | /* RCC_MP_AHB4ENCLRR register fields */ |
| 1242 | #define RCC_MP_AHB4ENCLRR_TSCEN BIT(15) |
| 1243 | |
| 1244 | /* RCC_MP_S_AHB4ENSETR register fields */ |
| 1245 | #define RCC_MP_S_AHB4ENSETR_GPIOAEN BIT(0) |
| 1246 | #define RCC_MP_S_AHB4ENSETR_GPIOBEN BIT(1) |
| 1247 | #define RCC_MP_S_AHB4ENSETR_GPIOCEN BIT(2) |
| 1248 | #define RCC_MP_S_AHB4ENSETR_GPIODEN BIT(3) |
| 1249 | #define RCC_MP_S_AHB4ENSETR_GPIOEEN BIT(4) |
| 1250 | #define RCC_MP_S_AHB4ENSETR_GPIOFEN BIT(5) |
| 1251 | #define RCC_MP_S_AHB4ENSETR_GPIOGEN BIT(6) |
| 1252 | #define RCC_MP_S_AHB4ENSETR_GPIOHEN BIT(7) |
| 1253 | #define RCC_MP_S_AHB4ENSETR_GPIOIEN BIT(8) |
| 1254 | |
| 1255 | /* RCC_MP_S_AHB4ENCLRR register fields */ |
| 1256 | #define RCC_MP_S_AHB4ENCLRR_GPIOAEN BIT(0) |
| 1257 | #define RCC_MP_S_AHB4ENCLRR_GPIOBEN BIT(1) |
| 1258 | #define RCC_MP_S_AHB4ENCLRR_GPIOCEN BIT(2) |
| 1259 | #define RCC_MP_S_AHB4ENCLRR_GPIODEN BIT(3) |
| 1260 | #define RCC_MP_S_AHB4ENCLRR_GPIOEEN BIT(4) |
| 1261 | #define RCC_MP_S_AHB4ENCLRR_GPIOFEN BIT(5) |
| 1262 | #define RCC_MP_S_AHB4ENCLRR_GPIOGEN BIT(6) |
| 1263 | #define RCC_MP_S_AHB4ENCLRR_GPIOHEN BIT(7) |
| 1264 | #define RCC_MP_S_AHB4ENCLRR_GPIOIEN BIT(8) |
| 1265 | |
| 1266 | /* RCC_MP_NS_AHB4ENSETR register fields */ |
| 1267 | #define RCC_MP_NS_AHB4ENSETR_GPIOAEN BIT(0) |
| 1268 | #define RCC_MP_NS_AHB4ENSETR_GPIOBEN BIT(1) |
| 1269 | #define RCC_MP_NS_AHB4ENSETR_GPIOCEN BIT(2) |
| 1270 | #define RCC_MP_NS_AHB4ENSETR_GPIODEN BIT(3) |
| 1271 | #define RCC_MP_NS_AHB4ENSETR_GPIOEEN BIT(4) |
| 1272 | #define RCC_MP_NS_AHB4ENSETR_GPIOFEN BIT(5) |
| 1273 | #define RCC_MP_NS_AHB4ENSETR_GPIOGEN BIT(6) |
| 1274 | #define RCC_MP_NS_AHB4ENSETR_GPIOHEN BIT(7) |
| 1275 | #define RCC_MP_NS_AHB4ENSETR_GPIOIEN BIT(8) |
| 1276 | |
| 1277 | /* RCC_MP_NS_AHB4ENCLRR register fields */ |
| 1278 | #define RCC_MP_NS_AHB4ENCLRR_GPIOAEN BIT(0) |
| 1279 | #define RCC_MP_NS_AHB4ENCLRR_GPIOBEN BIT(1) |
| 1280 | #define RCC_MP_NS_AHB4ENCLRR_GPIOCEN BIT(2) |
| 1281 | #define RCC_MP_NS_AHB4ENCLRR_GPIODEN BIT(3) |
| 1282 | #define RCC_MP_NS_AHB4ENCLRR_GPIOEEN BIT(4) |
| 1283 | #define RCC_MP_NS_AHB4ENCLRR_GPIOFEN BIT(5) |
| 1284 | #define RCC_MP_NS_AHB4ENCLRR_GPIOGEN BIT(6) |
| 1285 | #define RCC_MP_NS_AHB4ENCLRR_GPIOHEN BIT(7) |
| 1286 | #define RCC_MP_NS_AHB4ENCLRR_GPIOIEN BIT(8) |
| 1287 | |
| 1288 | /* RCC_MP_AHB5ENSETR register fields */ |
| 1289 | #define RCC_MP_AHB5ENSETR_PKAEN BIT(2) |
| 1290 | #define RCC_MP_AHB5ENSETR_SAESEN BIT(3) |
| 1291 | #define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) |
| 1292 | #define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) |
| 1293 | #define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) |
| 1294 | #define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) |
| 1295 | #define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) |
| 1296 | |
| 1297 | /* RCC_MP_AHB5ENCLRR register fields */ |
| 1298 | #define RCC_MP_AHB5ENCLRR_PKAEN BIT(2) |
| 1299 | #define RCC_MP_AHB5ENCLRR_SAESEN BIT(3) |
| 1300 | #define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) |
| 1301 | #define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) |
| 1302 | #define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) |
| 1303 | #define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) |
| 1304 | #define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) |
| 1305 | |
| 1306 | /* RCC_MP_AHB6ENSETR register fields */ |
| 1307 | #define RCC_MP_AHB6ENSETR_MCEEN BIT(1) |
| 1308 | #define RCC_MP_AHB6ENSETR_ETH1CKEN BIT(7) |
| 1309 | #define RCC_MP_AHB6ENSETR_ETH1TXEN BIT(8) |
| 1310 | #define RCC_MP_AHB6ENSETR_ETH1RXEN BIT(9) |
| 1311 | #define RCC_MP_AHB6ENSETR_ETH1MACEN BIT(10) |
| 1312 | #define RCC_MP_AHB6ENSETR_FMCEN BIT(12) |
| 1313 | #define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) |
| 1314 | #define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) |
| 1315 | #define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) |
| 1316 | #define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) |
| 1317 | #define RCC_MP_AHB6ENSETR_USBHEN BIT(24) |
| 1318 | #define RCC_MP_AHB6ENSETR_ETH2CKEN BIT(27) |
| 1319 | #define RCC_MP_AHB6ENSETR_ETH2TXEN BIT(28) |
| 1320 | #define RCC_MP_AHB6ENSETR_ETH2RXEN BIT(29) |
| 1321 | #define RCC_MP_AHB6ENSETR_ETH2MACEN BIT(30) |
| 1322 | |
| 1323 | /* RCC_MP_AHB6ENCLRR register fields */ |
| 1324 | #define RCC_MP_AHB6ENCLRR_MCEEN BIT(1) |
| 1325 | #define RCC_MP_AHB6ENCLRR_ETH1CKEN BIT(7) |
| 1326 | #define RCC_MP_AHB6ENCLRR_ETH1TXEN BIT(8) |
| 1327 | #define RCC_MP_AHB6ENCLRR_ETH1RXEN BIT(9) |
| 1328 | #define RCC_MP_AHB6ENCLRR_ETH1MACEN BIT(10) |
| 1329 | #define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) |
| 1330 | #define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) |
| 1331 | #define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) |
| 1332 | #define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) |
| 1333 | #define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) |
| 1334 | #define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) |
| 1335 | #define RCC_MP_AHB6ENCLRR_ETH2CKEN BIT(27) |
| 1336 | #define RCC_MP_AHB6ENCLRR_ETH2TXEN BIT(28) |
| 1337 | #define RCC_MP_AHB6ENCLRR_ETH2RXEN BIT(29) |
| 1338 | #define RCC_MP_AHB6ENCLRR_ETH2MACEN BIT(30) |
| 1339 | |
| 1340 | /* RCC_MP_S_AHB6ENSETR register fields */ |
| 1341 | #define RCC_MP_S_AHB6ENSETR_MDMAEN BIT(0) |
| 1342 | |
| 1343 | /* RCC_MP_S_AHB6ENCLRR register fields */ |
| 1344 | #define RCC_MP_S_AHB6ENCLRR_MDMAEN BIT(0) |
| 1345 | |
| 1346 | /* RCC_MP_NS_AHB6ENSETR register fields */ |
| 1347 | #define RCC_MP_NS_AHB6ENSETR_MDMAEN BIT(0) |
| 1348 | |
| 1349 | /* RCC_MP_NS_AHB6ENCLRR register fields */ |
| 1350 | #define RCC_MP_NS_AHB6ENCLRR_MDMAEN BIT(0) |
| 1351 | |
| 1352 | /* RCC_MP_APB1LPENSETR register fields */ |
| 1353 | #define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) |
| 1354 | #define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) |
| 1355 | #define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) |
| 1356 | #define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) |
| 1357 | #define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) |
| 1358 | #define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) |
| 1359 | #define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) |
| 1360 | #define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) |
| 1361 | #define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) |
| 1362 | #define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) |
| 1363 | #define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) |
| 1364 | #define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) |
| 1365 | #define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) |
| 1366 | #define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) |
| 1367 | #define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) |
| 1368 | #define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) |
| 1369 | #define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) |
| 1370 | |
| 1371 | /* RCC_MP_APB1LPENCLRR register fields */ |
| 1372 | #define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) |
| 1373 | #define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) |
| 1374 | #define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) |
| 1375 | #define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) |
| 1376 | #define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) |
| 1377 | #define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) |
| 1378 | #define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) |
| 1379 | #define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) |
| 1380 | #define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) |
| 1381 | #define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) |
| 1382 | #define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) |
| 1383 | #define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) |
| 1384 | #define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) |
| 1385 | #define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) |
| 1386 | #define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) |
| 1387 | #define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) |
| 1388 | #define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) |
| 1389 | |
| 1390 | /* RCC_MP_APB2LPENSETR register fields */ |
| 1391 | #define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) |
| 1392 | #define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) |
| 1393 | #define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) |
| 1394 | #define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) |
| 1395 | #define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) |
| 1396 | #define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) |
| 1397 | #define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) |
| 1398 | #define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) |
| 1399 | #define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) |
| 1400 | |
| 1401 | /* RCC_MP_APB2LPENCLRR register fields */ |
| 1402 | #define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) |
| 1403 | #define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) |
| 1404 | #define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) |
| 1405 | #define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) |
| 1406 | #define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) |
| 1407 | #define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) |
| 1408 | #define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) |
| 1409 | #define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) |
| 1410 | #define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) |
| 1411 | |
| 1412 | /* RCC_MP_APB3LPENSETR register fields */ |
| 1413 | #define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) |
| 1414 | #define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) |
| 1415 | #define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) |
| 1416 | #define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) |
| 1417 | #define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) |
| 1418 | #define RCC_MP_APB3LPENSETR_DTSLPEN BIT(16) |
| 1419 | #define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) |
| 1420 | |
| 1421 | /* RCC_MP_APB3LPENCLRR register fields */ |
| 1422 | #define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) |
| 1423 | #define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) |
| 1424 | #define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) |
| 1425 | #define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) |
| 1426 | #define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) |
| 1427 | #define RCC_MP_APB3LPENCLRR_DTSLPEN BIT(16) |
| 1428 | #define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) |
| 1429 | |
| 1430 | /* RCC_MP_S_APB3LPENSETR register fields */ |
| 1431 | #define RCC_MP_S_APB3LPENSETR_SYSCFGLPEN BIT(0) |
| 1432 | |
| 1433 | /* RCC_MP_S_APB3LPENCLRR register fields */ |
| 1434 | #define RCC_MP_S_APB3LPENCLRR_SYSCFGLPEN BIT(0) |
| 1435 | |
| 1436 | /* RCC_MP_NS_APB3LPENSETR register fields */ |
| 1437 | #define RCC_MP_NS_APB3LPENSETR_SYSCFGLPEN BIT(0) |
| 1438 | |
| 1439 | /* RCC_MP_NS_APB3LPENCLRR register fields */ |
| 1440 | #define RCC_MP_NS_APB3LPENCLRR_SYSCFGLPEN BIT(0) |
| 1441 | |
| 1442 | /* RCC_MP_APB4LPENSETR register fields */ |
| 1443 | #define RCC_MP_APB4LPENSETR_DCMIPPLPEN BIT(1) |
| 1444 | #define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) |
| 1445 | #define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) |
| 1446 | #define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) |
| 1447 | #define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) |
| 1448 | #define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) |
| 1449 | |
| 1450 | /* RCC_MP_APB4LPENCLRR register fields */ |
| 1451 | #define RCC_MP_APB4LPENCLRR_DCMIPPLPEN BIT(1) |
| 1452 | #define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) |
| 1453 | #define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) |
| 1454 | #define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) |
| 1455 | #define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) |
| 1456 | #define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) |
| 1457 | |
| 1458 | /* RCC_MP_S_APB4LPENSETR register fields */ |
| 1459 | #define RCC_MP_S_APB4LPENSETR_LTDCLPEN BIT(0) |
| 1460 | |
| 1461 | /* RCC_MP_S_APB4LPENCLRR register fields */ |
| 1462 | #define RCC_MP_S_APB4LPENCLRR_LTDCLPEN BIT(0) |
| 1463 | |
| 1464 | /* RCC_MP_NS_APB4LPENSETR register fields */ |
| 1465 | #define RCC_MP_NS_APB4LPENSETR_LTDCLPEN BIT(0) |
| 1466 | |
| 1467 | /* RCC_MP_NS_APB4LPENCLRR register fields */ |
| 1468 | #define RCC_MP_NS_APB4LPENCLRR_LTDCLPEN BIT(0) |
| 1469 | |
| 1470 | /* RCC_MP_APB5LPENSETR register fields */ |
| 1471 | #define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) |
| 1472 | #define RCC_MP_APB5LPENSETR_TZCLPEN BIT(11) |
| 1473 | #define RCC_MP_APB5LPENSETR_ETZPCLPEN BIT(13) |
| 1474 | #define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) |
| 1475 | #define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) |
| 1476 | #define RCC_MP_APB5LPENSETR_STGENCLPEN BIT(20) |
| 1477 | #define RCC_MP_APB5LPENSETR_STGENCSTPEN BIT(21) |
| 1478 | |
| 1479 | /* RCC_MP_APB5LPENCLRR register fields */ |
| 1480 | #define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) |
| 1481 | #define RCC_MP_APB5LPENCLRR_TZCLPEN BIT(11) |
| 1482 | #define RCC_MP_APB5LPENCLRR_ETZPCLPEN BIT(13) |
| 1483 | #define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) |
| 1484 | #define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) |
| 1485 | #define RCC_MP_APB5LPENCLRR_STGENCLPEN BIT(20) |
| 1486 | #define RCC_MP_APB5LPENCLRR_STGENCSTPEN BIT(21) |
| 1487 | |
| 1488 | /* RCC_MP_APB6LPENSETR register fields */ |
| 1489 | #define RCC_MP_APB6LPENSETR_USART1LPEN BIT(0) |
| 1490 | #define RCC_MP_APB6LPENSETR_USART2LPEN BIT(1) |
| 1491 | #define RCC_MP_APB6LPENSETR_SPI4LPEN BIT(2) |
| 1492 | #define RCC_MP_APB6LPENSETR_SPI5LPEN BIT(3) |
| 1493 | #define RCC_MP_APB6LPENSETR_I2C3LPEN BIT(4) |
| 1494 | #define RCC_MP_APB6LPENSETR_I2C4LPEN BIT(5) |
| 1495 | #define RCC_MP_APB6LPENSETR_I2C5LPEN BIT(6) |
| 1496 | #define RCC_MP_APB6LPENSETR_TIM12LPEN BIT(7) |
| 1497 | #define RCC_MP_APB6LPENSETR_TIM13LPEN BIT(8) |
| 1498 | #define RCC_MP_APB6LPENSETR_TIM14LPEN BIT(9) |
| 1499 | #define RCC_MP_APB6LPENSETR_TIM15LPEN BIT(10) |
| 1500 | #define RCC_MP_APB6LPENSETR_TIM16LPEN BIT(11) |
| 1501 | #define RCC_MP_APB6LPENSETR_TIM17LPEN BIT(12) |
| 1502 | |
| 1503 | /* RCC_MP_APB6LPENCLRR register fields */ |
| 1504 | #define RCC_MP_APB6LPENCLRR_USART1LPEN BIT(0) |
| 1505 | #define RCC_MP_APB6LPENCLRR_USART2LPEN BIT(1) |
| 1506 | #define RCC_MP_APB6LPENCLRR_SPI4LPEN BIT(2) |
| 1507 | #define RCC_MP_APB6LPENCLRR_SPI5LPEN BIT(3) |
| 1508 | #define RCC_MP_APB6LPENCLRR_I2C3LPEN BIT(4) |
| 1509 | #define RCC_MP_APB6LPENCLRR_I2C4LPEN BIT(5) |
| 1510 | #define RCC_MP_APB6LPENCLRR_I2C5LPEN BIT(6) |
| 1511 | #define RCC_MP_APB6LPENCLRR_TIM12LPEN BIT(7) |
| 1512 | #define RCC_MP_APB6LPENCLRR_TIM13LPEN BIT(8) |
| 1513 | #define RCC_MP_APB6LPENCLRR_TIM14LPEN BIT(9) |
| 1514 | #define RCC_MP_APB6LPENCLRR_TIM15LPEN BIT(10) |
| 1515 | #define RCC_MP_APB6LPENCLRR_TIM16LPEN BIT(11) |
| 1516 | #define RCC_MP_APB6LPENCLRR_TIM17LPEN BIT(12) |
| 1517 | |
| 1518 | /* RCC_MP_AHB2LPENSETR register fields */ |
| 1519 | #define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) |
| 1520 | #define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) |
| 1521 | #define RCC_MP_AHB2LPENSETR_DMAMUX1LPEN BIT(2) |
| 1522 | #define RCC_MP_AHB2LPENSETR_DMA3LPEN BIT(3) |
| 1523 | #define RCC_MP_AHB2LPENSETR_DMAMUX2LPEN BIT(4) |
| 1524 | #define RCC_MP_AHB2LPENSETR_ADC1LPEN BIT(5) |
| 1525 | #define RCC_MP_AHB2LPENSETR_ADC2LPEN BIT(6) |
| 1526 | #define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) |
| 1527 | |
| 1528 | /* RCC_MP_AHB2LPENCLRR register fields */ |
| 1529 | #define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) |
| 1530 | #define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) |
| 1531 | #define RCC_MP_AHB2LPENCLRR_DMAMUX1LPEN BIT(2) |
| 1532 | #define RCC_MP_AHB2LPENCLRR_DMA3LPEN BIT(3) |
| 1533 | #define RCC_MP_AHB2LPENCLRR_DMAMUX2LPEN BIT(4) |
| 1534 | #define RCC_MP_AHB2LPENCLRR_ADC1LPEN BIT(5) |
| 1535 | #define RCC_MP_AHB2LPENCLRR_ADC2LPEN BIT(6) |
| 1536 | #define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) |
| 1537 | |
| 1538 | /* RCC_MP_AHB4LPENSETR register fields */ |
| 1539 | #define RCC_MP_AHB4LPENSETR_TSCLPEN BIT(15) |
| 1540 | |
| 1541 | /* RCC_MP_AHB4LPENCLRR register fields */ |
| 1542 | #define RCC_MP_AHB4LPENCLRR_TSCLPEN BIT(15) |
| 1543 | |
| 1544 | /* RCC_MP_S_AHB4LPENSETR register fields */ |
| 1545 | #define RCC_MP_S_AHB4LPENSETR_GPIOALPEN BIT(0) |
| 1546 | #define RCC_MP_S_AHB4LPENSETR_GPIOBLPEN BIT(1) |
| 1547 | #define RCC_MP_S_AHB4LPENSETR_GPIOCLPEN BIT(2) |
| 1548 | #define RCC_MP_S_AHB4LPENSETR_GPIODLPEN BIT(3) |
| 1549 | #define RCC_MP_S_AHB4LPENSETR_GPIOELPEN BIT(4) |
| 1550 | #define RCC_MP_S_AHB4LPENSETR_GPIOFLPEN BIT(5) |
| 1551 | #define RCC_MP_S_AHB4LPENSETR_GPIOGLPEN BIT(6) |
| 1552 | #define RCC_MP_S_AHB4LPENSETR_GPIOHLPEN BIT(7) |
| 1553 | #define RCC_MP_S_AHB4LPENSETR_GPIOILPEN BIT(8) |
| 1554 | |
| 1555 | /* RCC_MP_S_AHB4LPENCLRR register fields */ |
| 1556 | #define RCC_MP_S_AHB4LPENCLRR_GPIOALPEN BIT(0) |
| 1557 | #define RCC_MP_S_AHB4LPENCLRR_GPIOBLPEN BIT(1) |
| 1558 | #define RCC_MP_S_AHB4LPENCLRR_GPIOCLPEN BIT(2) |
| 1559 | #define RCC_MP_S_AHB4LPENCLRR_GPIODLPEN BIT(3) |
| 1560 | #define RCC_MP_S_AHB4LPENCLRR_GPIOELPEN BIT(4) |
| 1561 | #define RCC_MP_S_AHB4LPENCLRR_GPIOFLPEN BIT(5) |
| 1562 | #define RCC_MP_S_AHB4LPENCLRR_GPIOGLPEN BIT(6) |
| 1563 | #define RCC_MP_S_AHB4LPENCLRR_GPIOHLPEN BIT(7) |
| 1564 | #define RCC_MP_S_AHB4LPENCLRR_GPIOILPEN BIT(8) |
| 1565 | |
| 1566 | /* RCC_MP_NS_AHB4LPENSETR register fields */ |
| 1567 | #define RCC_MP_NS_AHB4LPENSETR_GPIOALPEN BIT(0) |
| 1568 | #define RCC_MP_NS_AHB4LPENSETR_GPIOBLPEN BIT(1) |
| 1569 | #define RCC_MP_NS_AHB4LPENSETR_GPIOCLPEN BIT(2) |
| 1570 | #define RCC_MP_NS_AHB4LPENSETR_GPIODLPEN BIT(3) |
| 1571 | #define RCC_MP_NS_AHB4LPENSETR_GPIOELPEN BIT(4) |
| 1572 | #define RCC_MP_NS_AHB4LPENSETR_GPIOFLPEN BIT(5) |
| 1573 | #define RCC_MP_NS_AHB4LPENSETR_GPIOGLPEN BIT(6) |
| 1574 | #define RCC_MP_NS_AHB4LPENSETR_GPIOHLPEN BIT(7) |
| 1575 | #define RCC_MP_NS_AHB4LPENSETR_GPIOILPEN BIT(8) |
| 1576 | |
| 1577 | /* RCC_MP_NS_AHB4LPENCLRR register fields */ |
| 1578 | #define RCC_MP_NS_AHB4LPENCLRR_GPIOALPEN BIT(0) |
| 1579 | #define RCC_MP_NS_AHB4LPENCLRR_GPIOBLPEN BIT(1) |
| 1580 | #define RCC_MP_NS_AHB4LPENCLRR_GPIOCLPEN BIT(2) |
| 1581 | #define RCC_MP_NS_AHB4LPENCLRR_GPIODLPEN BIT(3) |
| 1582 | #define RCC_MP_NS_AHB4LPENCLRR_GPIOELPEN BIT(4) |
| 1583 | #define RCC_MP_NS_AHB4LPENCLRR_GPIOFLPEN BIT(5) |
| 1584 | #define RCC_MP_NS_AHB4LPENCLRR_GPIOGLPEN BIT(6) |
| 1585 | #define RCC_MP_NS_AHB4LPENCLRR_GPIOHLPEN BIT(7) |
| 1586 | #define RCC_MP_NS_AHB4LPENCLRR_GPIOILPEN BIT(8) |
| 1587 | |
| 1588 | /* RCC_MP_AHB5LPENSETR register fields */ |
| 1589 | #define RCC_MP_AHB5LPENSETR_PKALPEN BIT(2) |
| 1590 | #define RCC_MP_AHB5LPENSETR_SAESLPEN BIT(3) |
| 1591 | #define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) |
| 1592 | #define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) |
| 1593 | #define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) |
| 1594 | #define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) |
| 1595 | |
| 1596 | /* RCC_MP_AHB5LPENCLRR register fields */ |
| 1597 | #define RCC_MP_AHB5LPENCLRR_PKALPEN BIT(2) |
| 1598 | #define RCC_MP_AHB5LPENCLRR_SAESLPEN BIT(3) |
| 1599 | #define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) |
| 1600 | #define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) |
| 1601 | #define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) |
| 1602 | #define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) |
| 1603 | |
| 1604 | /* RCC_MP_AHB6LPENSETR register fields */ |
| 1605 | #define RCC_MP_AHB6LPENSETR_MCELPEN BIT(1) |
| 1606 | #define RCC_MP_AHB6LPENSETR_ETH1CKLPEN BIT(7) |
| 1607 | #define RCC_MP_AHB6LPENSETR_ETH1TXLPEN BIT(8) |
| 1608 | #define RCC_MP_AHB6LPENSETR_ETH1RXLPEN BIT(9) |
| 1609 | #define RCC_MP_AHB6LPENSETR_ETH1MACLPEN BIT(10) |
| 1610 | #define RCC_MP_AHB6LPENSETR_ETH1STPEN BIT(11) |
| 1611 | #define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) |
| 1612 | #define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) |
| 1613 | #define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) |
| 1614 | #define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) |
| 1615 | #define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) |
| 1616 | #define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) |
| 1617 | #define RCC_MP_AHB6LPENSETR_ETH2CKLPEN BIT(27) |
| 1618 | #define RCC_MP_AHB6LPENSETR_ETH2TXLPEN BIT(28) |
| 1619 | #define RCC_MP_AHB6LPENSETR_ETH2RXLPEN BIT(29) |
| 1620 | #define RCC_MP_AHB6LPENSETR_ETH2MACLPEN BIT(30) |
| 1621 | #define RCC_MP_AHB6LPENSETR_ETH2STPEN BIT(31) |
| 1622 | |
| 1623 | /* RCC_MP_AHB6LPENCLRR register fields */ |
| 1624 | #define RCC_MP_AHB6LPENCLRR_MCELPEN BIT(1) |
| 1625 | #define RCC_MP_AHB6LPENCLRR_ETH1CKLPEN BIT(7) |
| 1626 | #define RCC_MP_AHB6LPENCLRR_ETH1TXLPEN BIT(8) |
| 1627 | #define RCC_MP_AHB6LPENCLRR_ETH1RXLPEN BIT(9) |
| 1628 | #define RCC_MP_AHB6LPENCLRR_ETH1MACLPEN BIT(10) |
| 1629 | #define RCC_MP_AHB6LPENCLRR_ETH1STPEN BIT(11) |
| 1630 | #define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) |
| 1631 | #define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) |
| 1632 | #define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) |
| 1633 | #define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) |
| 1634 | #define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) |
| 1635 | #define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) |
| 1636 | #define RCC_MP_AHB6LPENCLRR_ETH2CKLPEN BIT(27) |
| 1637 | #define RCC_MP_AHB6LPENCLRR_ETH2TXLPEN BIT(28) |
| 1638 | #define RCC_MP_AHB6LPENCLRR_ETH2RXLPEN BIT(29) |
| 1639 | #define RCC_MP_AHB6LPENCLRR_ETH2MACLPEN BIT(30) |
| 1640 | #define RCC_MP_AHB6LPENCLRR_ETH2STPEN BIT(31) |
| 1641 | |
| 1642 | /* RCC_MP_S_AHB6LPENSETR register fields */ |
| 1643 | #define RCC_MP_S_AHB6LPENSETR_MDMALPEN BIT(0) |
| 1644 | |
| 1645 | /* RCC_MP_S_AHB6LPENCLRR register fields */ |
| 1646 | #define RCC_MP_S_AHB6LPENCLRR_MDMALPEN BIT(0) |
| 1647 | |
| 1648 | /* RCC_MP_NS_AHB6LPENSETR register fields */ |
| 1649 | #define RCC_MP_NS_AHB6LPENSETR_MDMALPEN BIT(0) |
| 1650 | |
| 1651 | /* RCC_MP_NS_AHB6LPENCLRR register fields */ |
| 1652 | #define RCC_MP_NS_AHB6LPENCLRR_MDMALPEN BIT(0) |
| 1653 | |
| 1654 | /* RCC_MP_S_AXIMLPENSETR register fields */ |
| 1655 | #define RCC_MP_S_AXIMLPENSETR_SYSRAMLPEN BIT(0) |
| 1656 | |
| 1657 | /* RCC_MP_S_AXIMLPENCLRR register fields */ |
| 1658 | #define RCC_MP_S_AXIMLPENCLRR_SYSRAMLPEN BIT(0) |
| 1659 | |
| 1660 | /* RCC_MP_NS_AXIMLPENSETR register fields */ |
| 1661 | #define RCC_MP_NS_AXIMLPENSETR_SYSRAMLPEN BIT(0) |
| 1662 | |
| 1663 | /* RCC_MP_NS_AXIMLPENCLRR register fields */ |
| 1664 | #define RCC_MP_NS_AXIMLPENCLRR_SYSRAMLPEN BIT(0) |
| 1665 | |
| 1666 | /* RCC_MP_MLAHBLPENSETR register fields */ |
| 1667 | #define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) |
| 1668 | #define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) |
| 1669 | #define RCC_MP_MLAHBLPENSETR_SRAM3LPEN BIT(2) |
| 1670 | |
| 1671 | /* RCC_MP_MLAHBLPENCLRR register fields */ |
| 1672 | #define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) |
| 1673 | #define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) |
| 1674 | #define RCC_MP_MLAHBLPENCLRR_SRAM3LPEN BIT(2) |
| 1675 | |
| 1676 | /* RCC_APB3SECSR register fields */ |
| 1677 | #define RCC_APB3SECSR_LPTIM2SECF BIT(0) |
| 1678 | #define RCC_APB3SECSR_LPTIM3SECF BIT(1) |
| 1679 | #define RCC_APB3SECSR_VREFSECF BIT(13) |
| 1680 | |
| 1681 | /* RCC_APB4SECSR register fields */ |
| 1682 | #define RCC_APB4SECSR_DCMIPPSECF BIT(1) |
| 1683 | #define RCC_APB4SECSR_USBPHYSECF BIT(16) |
| 1684 | |
| 1685 | /* RCC_APB5SECSR register fields */ |
| 1686 | #define RCC_APB5SECSR_RTCSECF BIT(8) |
| 1687 | #define RCC_APB5SECSR_TZCSECF BIT(11) |
| 1688 | #define RCC_APB5SECSR_ETZPCSECF BIT(13) |
| 1689 | #define RCC_APB5SECSR_IWDG1SECF BIT(15) |
| 1690 | #define RCC_APB5SECSR_BSECSECF BIT(16) |
| 1691 | #define RCC_APB5SECSR_STGENCSECF_MASK GENMASK(21, 20) |
| 1692 | #define RCC_APB5SECSR_STGENCSECF_SHIFT 20 |
| 1693 | |
| 1694 | /* RCC_APB6SECSR register fields */ |
| 1695 | #define RCC_APB6SECSR_USART1SECF BIT(0) |
| 1696 | #define RCC_APB6SECSR_USART2SECF BIT(1) |
| 1697 | #define RCC_APB6SECSR_SPI4SECF BIT(2) |
| 1698 | #define RCC_APB6SECSR_SPI5SECF BIT(3) |
| 1699 | #define RCC_APB6SECSR_I2C3SECF BIT(4) |
| 1700 | #define RCC_APB6SECSR_I2C4SECF BIT(5) |
| 1701 | #define RCC_APB6SECSR_I2C5SECF BIT(6) |
| 1702 | #define RCC_APB6SECSR_TIM12SECF BIT(7) |
| 1703 | #define RCC_APB6SECSR_TIM13SECF BIT(8) |
| 1704 | #define RCC_APB6SECSR_TIM14SECF BIT(9) |
| 1705 | #define RCC_APB6SECSR_TIM15SECF BIT(10) |
| 1706 | #define RCC_APB6SECSR_TIM16SECF BIT(11) |
| 1707 | #define RCC_APB6SECSR_TIM17SECF BIT(12) |
| 1708 | |
| 1709 | /* RCC_AHB2SECSR register fields */ |
| 1710 | #define RCC_AHB2SECSR_DMA3SECF BIT(3) |
| 1711 | #define RCC_AHB2SECSR_DMAMUX2SECF BIT(4) |
| 1712 | #define RCC_AHB2SECSR_ADC1SECF BIT(5) |
| 1713 | #define RCC_AHB2SECSR_ADC2SECF BIT(6) |
| 1714 | #define RCC_AHB2SECSR_USBOSECF BIT(8) |
| 1715 | |
| 1716 | /* RCC_AHB4SECSR register fields */ |
| 1717 | #define RCC_AHB4SECSR_TSCSECF BIT(15) |
| 1718 | |
| 1719 | /* RCC_AHB5SECSR register fields */ |
| 1720 | #define RCC_AHB5SECSR_PKASECF BIT(2) |
| 1721 | #define RCC_AHB5SECSR_SAESSECF BIT(3) |
| 1722 | #define RCC_AHB5SECSR_CRYP1SECF BIT(4) |
| 1723 | #define RCC_AHB5SECSR_HASH1SECF BIT(5) |
| 1724 | #define RCC_AHB5SECSR_RNG1SECF BIT(6) |
| 1725 | #define RCC_AHB5SECSR_BKPSRAMSECF BIT(8) |
| 1726 | |
| 1727 | /* RCC_AHB6SECSR register fields */ |
| 1728 | #define RCC_AHB6SECSR_MCESECF BIT(1) |
| 1729 | #define RCC_AHB6SECSR_ETH1SECF_MASK GENMASK(11, 7) |
| 1730 | #define RCC_AHB6SECSR_ETH1SECF_SHIFT 7 |
| 1731 | #define RCC_AHB6SECSR_FMCSECF BIT(12) |
| 1732 | #define RCC_AHB6SECSR_QSPISECF BIT(14) |
| 1733 | #define RCC_AHB6SECSR_SDMMC1SECF BIT(16) |
| 1734 | #define RCC_AHB6SECSR_SDMMC2SECF BIT(17) |
| 1735 | #define RCC_AHB6SECSR_ETH2SECF_MASK GENMASK(31, 27) |
| 1736 | #define RCC_AHB6SECSR_ETH2SECF_SHIFT 27 |
| 1737 | |
| 1738 | /* RCC_VERR register fields */ |
| 1739 | #define RCC_VERR_MINREV_MASK GENMASK(3, 0) |
| 1740 | #define RCC_VERR_MINREV_SHIFT 0 |
| 1741 | #define RCC_VERR_MAJREV_MASK GENMASK(7, 4) |
| 1742 | #define RCC_VERR_MAJREV_SHIFT 4 |
| 1743 | |
| 1744 | /* RCC_IDR register fields */ |
| 1745 | #define RCC_IDR_ID_MASK GENMASK(31, 0) |
| 1746 | #define RCC_IDR_ID_SHIFT 0 |
| 1747 | |
| 1748 | /* RCC_SIDR register fields */ |
| 1749 | #define RCC_SIDR_SID_MASK GENMASK(31, 0) |
| 1750 | #define RCC_SIDR_SID_SHIFT 0 |
| 1751 | |
| 1752 | /* Used for all RCC_PLL<n>CR registers */ |
| 1753 | #define RCC_PLLNCR_PLLON BIT(0) |
| 1754 | #define RCC_PLLNCR_PLLRDY BIT(1) |
| 1755 | #define RCC_PLLNCR_SSCG_CTRL BIT(2) |
| 1756 | #define RCC_PLLNCR_DIVPEN BIT(4) |
| 1757 | #define RCC_PLLNCR_DIVQEN BIT(5) |
| 1758 | #define RCC_PLLNCR_DIVREN BIT(6) |
| 1759 | #define RCC_PLLNCR_DIVEN_SHIFT 4 |
| 1760 | |
| 1761 | /* Used for all RCC_PLL<n>CFGR1 registers */ |
| 1762 | #define RCC_PLLNCFGR1_DIVM_SHIFT 16 |
| 1763 | #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) |
| 1764 | #define RCC_PLLNCFGR1_DIVN_SHIFT 0 |
| 1765 | #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) |
| 1766 | |
| 1767 | /* Only for PLL3 and PLL4 */ |
| 1768 | #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 |
| 1769 | #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) |
| 1770 | |
| 1771 | /* Used for all RCC_PLL<n>CFGR2 registers */ |
| 1772 | #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) |
| 1773 | #define RCC_PLLNCFGR2_DIVP_SHIFT 0 |
| 1774 | #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) |
| 1775 | #define RCC_PLLNCFGR2_DIVQ_SHIFT 8 |
| 1776 | #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) |
| 1777 | #define RCC_PLLNCFGR2_DIVR_SHIFT 16 |
| 1778 | #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) |
| 1779 | |
| 1780 | /* Used for all RCC_PLL<n>FRACR registers */ |
| 1781 | #define RCC_PLLNFRACR_FRACV_SHIFT 3 |
| 1782 | #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) |
| 1783 | #define RCC_PLLNFRACR_FRACLE BIT(16) |
| 1784 | |
| 1785 | /* Used for all RCC_PLL<n>CSGR registers */ |
| 1786 | #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 |
| 1787 | #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) |
| 1788 | #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 |
| 1789 | #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) |
| 1790 | #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 |
| 1791 | #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) |
| 1792 | |
| 1793 | /* Used for most of RCC_<x>SELR registers */ |
| 1794 | #define RCC_SELR_SRC_MASK GENMASK(2, 0) |
| 1795 | #define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) |
| 1796 | #define RCC_SELR_SRCRDY BIT(31) |
| 1797 | |
| 1798 | /* Values of RCC_MPCKSELR register */ |
| 1799 | #define RCC_MPCKSELR_HSI 0x00000000 |
| 1800 | #define RCC_MPCKSELR_HSE 0x00000001 |
| 1801 | #define RCC_MPCKSELR_PLL 0x00000002 |
| 1802 | #define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 |
| 1803 | |
| 1804 | /* Values of RCC_ASSCKSELR register */ |
| 1805 | #define RCC_ASSCKSELR_HSI 0x00000000 |
| 1806 | #define RCC_ASSCKSELR_HSE 0x00000001 |
| 1807 | #define RCC_ASSCKSELR_PLL 0x00000002 |
| 1808 | |
| 1809 | /* Values of RCC_MSSCKSELR register */ |
| 1810 | #define RCC_MSSCKSELR_HSI 0x00000000 |
| 1811 | #define RCC_MSSCKSELR_HSE 0x00000001 |
| 1812 | #define RCC_MSSCKSELR_CSI 0x00000002 |
| 1813 | #define RCC_MSSCKSELR_PLL 0x00000003 |
| 1814 | |
| 1815 | /* Values of RCC_CPERCKSELR register */ |
| 1816 | #define RCC_CPERCKSELR_HSI 0x00000000 |
| 1817 | #define RCC_CPERCKSELR_CSI 0x00000001 |
| 1818 | #define RCC_CPERCKSELR_HSE 0x00000002 |
| 1819 | |
| 1820 | /* Used for most of DIVR register: max div for RTC */ |
| 1821 | #define RCC_DIVR_DIV_MASK GENMASK(5, 0) |
| 1822 | #define RCC_DIVR_DIVRDY BIT(31) |
| 1823 | |
| 1824 | /* Masks for specific DIVR registers */ |
| 1825 | #define RCC_APBXDIV_MASK GENMASK(2, 0) |
| 1826 | #define RCC_MPUDIV_MASK GENMASK(2, 0) |
| 1827 | #define RCC_AXIDIV_MASK GENMASK(2, 0) |
| 1828 | #define RCC_MLAHBDIV_MASK GENMASK(3, 0) |
| 1829 | |
| 1830 | /* Used for TIMER Prescaler */ |
| 1831 | #define RCC_TIMGXPRER_TIMGXPRE BIT(0) |
| 1832 | |
| 1833 | /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ |
| 1834 | #define RCC_MP_ENCLRR_OFFSET U(4) |
| 1835 | |
| 1836 | /* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ |
| 1837 | #define RCC_RSTCLRR_OFFSET U(4) |
| 1838 | |
| 1839 | /* RCC_OCENSETR register fields */ |
| 1840 | #define RCC_OCENR_HSION BIT(0) |
| 1841 | #define RCC_OCENR_HSIKERON BIT(1) |
| 1842 | #define RCC_OCENR_CSION BIT(4) |
| 1843 | #define RCC_OCENR_CSIKERON BIT(5) |
| 1844 | #define RCC_OCENR_DIGBYP BIT(7) |
| 1845 | #define RCC_OCENR_HSEON BIT(8) |
| 1846 | #define RCC_OCENR_HSEKERON BIT(9) |
| 1847 | #define RCC_OCENR_HSEBYP BIT(10) |
| 1848 | #define RCC_OCENR_HSECSSON BIT(11) |
| 1849 | |
| 1850 | #define RCC_OCENR_DIGBYP_BIT 7 |
| 1851 | #define RCC_OCENR_HSEBYP_BIT 10 |
| 1852 | #define RCC_OCENR_HSECSSON_BIT 11 |
| 1853 | |
| 1854 | /* Used for RCC_MCO related operations */ |
| 1855 | #define RCC_MCOCFG_MCOON BIT(12) |
| 1856 | #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) |
| 1857 | #define RCC_MCOCFG_MCODIV_SHIFT 4 |
| 1858 | #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) |
| 1859 | |
| 1860 | #define RCC_UART4CKSELR_HSI 0x00000002 |
| 1861 | |
| 1862 | #define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0) |
| 1863 | #define RCC_CPERCKSELR_PERSRC_SHIFT 0 |
| 1864 | |
| 1865 | #define RCC_USBCKSELR_USBOSRC_MASK BIT(4) |
| 1866 | #define RCC_USBCKSELR_USBOSRC_SHIFT 4 |
| 1867 | |
| 1868 | #define RCC_DDRITFCR_DDRCKMOD_SSR 0 |
| 1869 | #define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) |
| 1870 | #define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) |
| 1871 | |
| 1872 | #define RCC_DDRITFCR_DDRC2EN BIT(0) |
| 1873 | #define RCC_DDRITFCR_DDRC2LPEN BIT(1) |
| 1874 | |
| 1875 | #define RCC_MP_CIFR_MASK U(0x110F1F) |
| 1876 | #define RCC_OFFSET_MASK GENMASK(11, 0) |
| 1877 | |
| 1878 | #endif /* STM32MP1_RCC_H */ |