| Nicolas Le Bayon | 97287cd | 2019-05-20 18:35:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef BSEC2_REG_H |
| 8 | #define BSEC2_REG_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /* IP configuration */ |
| 13 | #define ADDR_LOWER_OTP_PERLOCK_SHIFT 0x03 |
| 14 | #define DATA_LOWER_OTP_PERLOCK_BIT 0x03U /* 2 significants bits are used */ |
| 15 | #define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0) |
| 16 | #define ADDR_UPPER_OTP_PERLOCK_SHIFT 0x04 |
| 17 | #define DATA_UPPER_OTP_PERLOCK_BIT 0x01U /* 1 significants bits are used */ |
| 18 | #define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0) |
| 19 | |
| 20 | /* BSEC REGISTER OFFSET (base relative) */ |
| 21 | #define BSEC_OTP_CONF_OFF U(0x000) |
| 22 | #define BSEC_OTP_CTRL_OFF U(0x004) |
| 23 | #define BSEC_OTP_WRDATA_OFF U(0x008) |
| 24 | #define BSEC_OTP_STATUS_OFF U(0x00C) |
| 25 | #define BSEC_OTP_LOCK_OFF U(0x010) |
| 26 | #define BSEC_DEN_OFF U(0x014) |
| 27 | #define BSEC_DISTURBED_OFF U(0x01C) |
| 28 | #define BSEC_DISTURBED1_OFF U(0x020) |
| 29 | #define BSEC_DISTURBED2_OFF U(0x024) |
| 30 | #define BSEC_ERROR_OFF U(0x034) |
| 31 | #define BSEC_ERROR1_OFF U(0x038) |
| 32 | #define BSEC_ERROR2_OFF U(0x03C) |
| 33 | #define BSEC_WRLOCK_OFF U(0x04C) /* Safmem permanent lock */ |
| 34 | #define BSEC_WRLOCK1_OFF U(0x050) |
| 35 | #define BSEC_WRLOCK2_OFF U(0x054) |
| 36 | #define BSEC_SPLOCK_OFF U(0x064) /* Program safmem sticky lock */ |
| 37 | #define BSEC_SPLOCK1_OFF U(0x068) |
| 38 | #define BSEC_SPLOCK2_OFF U(0x06C) |
| 39 | #define BSEC_SWLOCK_OFF U(0x07C) /* Write in OTP sticky lock */ |
| 40 | #define BSEC_SWLOCK1_OFF U(0x080) |
| 41 | #define BSEC_SWLOCK2_OFF U(0x084) |
| 42 | #define BSEC_SRLOCK_OFF U(0x094) /* Shadowing sticky lock */ |
| 43 | #define BSEC_SRLOCK1_OFF U(0x098) |
| 44 | #define BSEC_SRLOCK2_OFF U(0x09C) |
| 45 | #define BSEC_JTAG_IN_OFF U(0x0AC) |
| 46 | #define BSEC_JTAG_OUT_OFF U(0x0B0) |
| 47 | #define BSEC_SCRATCH_OFF U(0x0B4) |
| 48 | #define BSEC_OTP_DATA_OFF U(0x200) |
| 49 | #define BSEC_IPHW_CFG_OFF U(0xFF0) |
| 50 | #define BSEC_IPVR_OFF U(0xFF4) |
| 51 | #define BSEC_IP_ID_OFF U(0xFF8) |
| 52 | #define BSEC_IP_MAGIC_ID_OFF U(0xFFC) |
| 53 | |
| 54 | #define BSEC_WRLOCK(n) (BSEC_WRLOCK_OFF + U(0x04) * (n)) |
| 55 | #define BSEC_SPLOCK(n) (BSEC_SPLOCK_OFF + U(0x04) * (n)) |
| 56 | #define BSEC_SWLOCK(n) (BSEC_SWLOCK_OFF + U(0x04) * (n)) |
| 57 | #define BSEC_SRLOCK(n) (BSEC_SRLOCK_OFF + U(0x04) * (n)) |
| 58 | |
| 59 | /* BSEC_CONFIGURATION Register */ |
| 60 | #define BSEC_CONF_POWER_UP_MASK BIT(0) |
| 61 | #define BSEC_CONF_POWER_UP_SHIFT 0 |
| 62 | #define BSEC_CONF_FRQ_MASK GENMASK(2, 1) |
| 63 | #define BSEC_CONF_FRQ_SHIFT 1 |
| 64 | #define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3) |
| 65 | #define BSEC_CONF_PRG_WIDTH_SHIFT 3 |
| 66 | #define BSEC_CONF_TREAD_MASK GENMASK(8, 7) |
| 67 | #define BSEC_CONF_TREAD_SHIFT 7 |
| 68 | |
| 69 | /* BSEC_CONTROL Register */ |
| 70 | #define BSEC_READ 0U |
| 71 | #define BSEC_WRITE BIT(8) |
| 72 | #define BSEC_LOCK BIT(9) |
| 73 | |
| 74 | /* BSEC_OTP_LOCK register */ |
| 75 | #define UPPER_OTP_LOCK_MASK BIT(0) |
| 76 | #define UPPER_OTP_LOCK_SHIFT 0 |
| 77 | #define DENREG_LOCK_MASK BIT(2) |
| 78 | #define DENREG_LOCK_SHIFT 2 |
| 79 | #define GPLOCK_LOCK_MASK BIT(4) |
| 80 | #define GPLOCK_LOCK_SHIFT 4 |
| 81 | |
| 82 | /* BSEC_OTP_STATUS Register */ |
| 83 | #define BSEC_MODE_STATUS_MASK GENMASK(2, 0) |
| 84 | #define BSEC_MODE_SECURE_MASK BIT(0) |
| 85 | #define BSEC_MODE_FULLDBG_MASK BIT(1) |
| 86 | #define BSEC_MODE_INVALID_MASK BIT(2) |
| 87 | #define BSEC_MODE_BUSY_MASK BIT(3) |
| 88 | #define BSEC_MODE_PROGFAIL_MASK BIT(4) |
| 89 | #define BSEC_MODE_PWR_MASK BIT(5) |
| 90 | #define BSEC_MODE_BIST1_LOCK_MASK BIT(6) |
| 91 | #define BSEC_MODE_BIST2_LOCK_MASK BIT(7) |
| 92 | |
| 93 | /* BSEC_DENABLE Register */ |
| 94 | #define BSEC_HDPEN BIT(4) |
| 95 | #define BSEC_SPIDEN BIT(5) |
| 96 | #define BSEC_SPINDEN BIT(6) |
| 97 | #define BSEC_DBGSWGEN BIT(10) |
| 98 | #define BSEC_DEN_ALL_MSK GENMASK(10, 0) |
| 99 | |
| 100 | /* BSEC_FENABLE Register */ |
| 101 | #define BSEC_FEN_ALL_MSK GENMASK(14, 0) |
| 102 | |
| 103 | /* BSEC_IPVR Register */ |
| 104 | #define BSEC_IPVR_MSK GENMASK(7, 0) |
| 105 | |
| 106 | #endif /* BSEC2_REG_H */ |