blob: 2498430c49734f649f58efb47cf80aeb678acc90 [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __SGM_BASE_PLATFORM_DEF_H__
8#define __SGM_BASE_PLATFORM_DEF_H__
9
10#include <arm_def.h>
11#include <board_arm_def.h>
12#include <board_css_def.h>
13#include <common_def.h>
14#include <css_def.h>
15#include <soc_css_def.h>
16#include <tzc400.h>
17#include <tzc_common.h>
18
19/* CPU topology */
20#define PLAT_ARM_CLUSTER_COUNT 1
21#define PLAT_ARM_CLUSTER_CORE_COUNT 8
22#define PLATFORM_CORE_COUNT PLAT_ARM_CLUSTER_CORE_COUNT
23
24#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
25#define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \
26 PLAT_ARM_CLUSTER_COUNT + \
27 PLATFORM_CORE_COUNT)
28
29/*
30 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
31 * terminology. On a GICv2 system or mode, the lists will be merged and treated
32 * as Group 0 interrupts.
33 */
34#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
35 CSS_G1S_IRQ_PROPS(grp), \
36 ARM_G1S_IRQ_PROPS(grp)
37
38#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
39
40/* GIC related constants */
41#define PLAT_ARM_GICD_BASE 0x30000000
42#define PLAT_ARM_GICR_BASE 0x300C0000
43#define PLAT_ARM_GICC_BASE 0x2c000000
44
45#define CSS_GIC_SIZE 0x00200000
46
47#define CSS_MAP_GIC_DEVICE MAP_REGION_FLAT( \
48 PLAT_ARM_GICD_BASE, \
49 CSS_GIC_SIZE, \
50 MT_DEVICE | MT_RW | MT_SECURE)
51
52/* Platform ID address */
53#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
54#ifndef __ASSEMBLY__
55/* SSC_VERSION related accessors */
56/* Returns the part number of the platform */
57#define GET_PLAT_PART_NUM \
58 GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
59/* Returns the configuration number of the platform */
60#define GET_PLAT_CONFIG_NUM \
61 GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
62#endif /* __ASSEMBLY__ */
63
64
65/*************************************************************************
66 * Definitions common to all SGM CSS based platforms
67 *************************************************************************/
68
69/* TZC-400 related constants */
70#define PLAT_ARM_TZC_BASE 0x2a500000
71#define TZC_NSAID_ALL_AP 0 /* Note: Same as default NSAID!! */
72#define TZC_NSAID_HDLCD0 2
73#define TZC_NSAID_HDLCD1 3
74#define TZC_NSAID_GPU 9
75#define TZC_NSAID_VIDEO 10
76#define TZC_NSAID_DISP0 11
77#define TZC_NSAID_DISP1 12
78
79
80/*************************************************************************
81 * Required platform porting definitions common to all SGM CSS based
82 * platforms
83 *************************************************************************/
84
85/* MHU related constants */
86#define PLAT_CSS_MHU_BASE 0x2b1f0000
87
88#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
89#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000
90
91#define PLAT_ARM_CCI_BASE 0x2a000000
92
93/* Cluster to CCI slave mapping */
94#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 6
95#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
96
97/* System timer related constants */
98#define PLAT_ARM_NSTIMER_FRAME_ID 0
99
100/* TZC related constants */
101#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
102 TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP) | \
103 TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0) | \
104 TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD1) | \
105 TZC_REGION_ACCESS_RDWR(TZC_NSAID_GPU) | \
106 TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIDEO) | \
107 TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP0) | \
108 TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP1))
109
110/* Display Processor register definitions to setup the NSAIDs */
111#define MALI_DP_BASE 0x2cc00000
112#define DP_NPROT_NSAID_OFFSET 0x1000c
113#define W_NPROT_NSAID_SHIFT 24
114#define LS_NPORT_NSAID_SHIFT 12
115
116/*
117 * Base address of the first memory region used for communication between AP
118 * and SCP. Used by the BootOverMHU and SCPI protocols.
119 */
120#if !CSS_USE_SCMI_SDS_DRIVER
121/*
122 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
123 * means the SCP/AP configuration data gets overwritten when the AP initiates
124 * communication with the SCP. The configuration data is expected to be a
125 * 32-bit word on all CSS platforms. Part of this configuration is
126 * which CPU is the primary, according to the shift and mask definitions below.
127 */
128#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80)
129#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
130#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4
131#endif
132
133/*
134 * tspd support is conditional so enable this for CSS sgm platforms.
135 */
136#define SPD_tspd
137
138/*
139 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
140 * SCP_BL2 size plus a little space for growth.
141 */
142#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x15000
143
144/*
145 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
146 * SCP_BL2U size plus a little space for growth.
147 */
148#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x15000
149
150/*
151 * Most platform porting definitions provided by included headers
152 */
153
154/*
155 * If ARM_BOARD_OPTIMISE_MEM=0 then use the default, unoptimised values
156 * defined for ARM development platforms.
157 */
158#if ARM_BOARD_OPTIMISE_MEM
159/*
160 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
161 * plat_arm_mmap array defined for each BL stage.
162 */
163#if IMAGE_BL1
164# if TRUSTED_BOARD_BOOT
165# define PLAT_ARM_MMAP_ENTRIES 7
166# else
167# define PLAT_ARM_MMAP_ENTRIES 6
168# endif /* TRUSTED_BOARD_BOOT */
169#elif IMAGE_BL2
170# define PLAT_ARM_MMAP_ENTRIES 8
171#elif IMAGE_BL2U
172# define PLAT_ARM_MMAP_ENTRIES 4
173#elif IMAGE_BL31
174# define PLAT_ARM_MMAP_ENTRIES 6
175#elif IMAGE_BL32
176# define PLAT_ARM_MMAP_ENTRIES 5
177#endif
178
179/*
180 * Platform specific page table and MMU setup constants
181 */
182#if IMAGE_BL1
183# if TRUSTED_BOARD_BOOT
184# define MAX_XLAT_TABLES 4
185# else
186# define MAX_XLAT_TABLES 3
187#endif
188#elif IMAGE_BL2
189# define MAX_XLAT_TABLES 4
190#elif IMAGE_BL2U
191# define MAX_XLAT_TABLES 4
192#elif IMAGE_BL31
193# define MAX_XLAT_TABLES 2
194#elif IMAGE_BL32
195# if ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
196# define MAX_XLAT_TABLES 3
197# else
198# define MAX_XLAT_TABLES 2
199# endif
200#endif
201
202/*
203 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
204 * plus a little space for growth.
205 */
206#if TRUSTED_BOARD_BOOT
207# define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000
208#else
209# define PLAT_ARM_MAX_BL1_RW_SIZE 0x7000
210#endif
211
212/*
213 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
214 * little space for growth.
215 */
216#if TRUSTED_BOARD_BOOT
217# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
218#else
219# define PLAT_ARM_MAX_BL2_SIZE 0xD000
220#endif
221
222#endif /* ARM_BOARD_OPTIMISE_MEM */
223
224/*******************************************************************************
225 * Memprotect definitions
226 ******************************************************************************/
227/* PSCI memory protect definitions:
228 * This variable is stored in a non-secure flash because some ARM reference
229 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
230 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
231 */
232#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
233 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
234#endif /* __SGM_BASE_PLATFORM_DEF_H__ */