blob: 277f11b7799377b3984b501540057e9c42656241 [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001/*
Toshiyuki Ogasaharaafab55c2021-07-12 18:30:07 +09002 * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CPG_REGISTERS_H
8#define CPG_REGISTERS_H
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02009
10/* CPG base address */
11#define CPG_BASE (0xE6150000U)
12
13/* CPG system module stop control 2 */
14#define CPG_SMSTPCR2 (CPG_BASE + 0x0138U)
15/* CPG software reset 2 */
16#define CPG_SRCR2 (CPG_BASE + 0x00B0U)
17/* CPG module stop status 2 */
18#define CPG_MSTPSR2 (CPG_BASE + 0x0040U)
Toshiyuki Ogasaharaafab55c2021-07-12 18:30:07 +090019/* CPG module stop status 3 */
Toshiyuki Ogasahara77626582020-11-30 20:39:21 +090020#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020021/* CPG write protect */
22#define CPG_CPGWPR (CPG_BASE + 0x0900U)
23/* CPG write protect control */
24#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
25/* CPG system module stop control 9 */
26#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U)
27/* CPG module stop status 9 */
28#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U)
Toshiyuki Ogasahara77626582020-11-30 20:39:21 +090029/* SDHI2 clock frequency control register */
30#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
31/* SDHI3 clock frequency control register */
32#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020033
34/* CPG (SECURITY) registers */
35
36/* Secure Module Stop Control Register 0 */
37#define SCMSTPCR0 (CPG_BASE + 0x0B20U)
38/* Secure Module Stop Control Register 1 */
39#define SCMSTPCR1 (CPG_BASE + 0x0B24U)
40/* Secure Module Stop Control Register 2 */
41#define SCMSTPCR2 (CPG_BASE + 0x0B28U)
42/* Secure Module Stop Control Register 3 */
43#define SCMSTPCR3 (CPG_BASE + 0x0B2CU)
44/* Secure Module Stop Control Register 4 */
45#define SCMSTPCR4 (CPG_BASE + 0x0B30U)
46/* Secure Module Stop Control Register 5 */
47#define SCMSTPCR5 (CPG_BASE + 0x0B34U)
48/* Secure Module Stop Control Register 6 */
49#define SCMSTPCR6 (CPG_BASE + 0x0B38U)
50/* Secure Module Stop Control Register 7 */
51#define SCMSTPCR7 (CPG_BASE + 0x0B3CU)
52/* Secure Module Stop Control Register 8 */
53#define SCMSTPCR8 (CPG_BASE + 0x0B40U)
54/* Secure Module Stop Control Register 9 */
55#define SCMSTPCR9 (CPG_BASE + 0x0B44U)
56/* Secure Module Stop Control Register 10 */
57#define SCMSTPCR10 (CPG_BASE + 0x0B48U)
58/* Secure Module Stop Control Register 11 */
59#define SCMSTPCR11 (CPG_BASE + 0x0B4CU)
60
61/* CPG (SECURITY) registers */
62
63/* Secure Software Reset Access Enable Control Register 0 */
64#define SCSRSTECR0 (CPG_BASE + 0x0B80U)
65/* Secure Software Reset Access Enable Control Register 1 */
66#define SCSRSTECR1 (CPG_BASE + 0x0B84U)
67/* Secure Software Reset Access Enable Control Register 2 */
68#define SCSRSTECR2 (CPG_BASE + 0x0B88U)
69/* Secure Software Reset Access Enable Control Register 3 */
70#define SCSRSTECR3 (CPG_BASE + 0x0B8CU)
71/* Secure Software Reset Access Enable Control Register 4 */
72#define SCSRSTECR4 (CPG_BASE + 0x0B90U)
73/* Secure Software Reset Access Enable Control Register 5 */
74#define SCSRSTECR5 (CPG_BASE + 0x0B94U)
75/* Secure Software Reset Access Enable Control Register 6 */
76#define SCSRSTECR6 (CPG_BASE + 0x0B98U)
77/* Secure Software Reset Access Enable Control Register 7 */
78#define SCSRSTECR7 (CPG_BASE + 0x0B9CU)
79/* Secure Software Reset Access Enable Control Register 8 */
80#define SCSRSTECR8 (CPG_BASE + 0x0BA0U)
81/* Secure Software Reset Access Enable Control Register 9 */
82#define SCSRSTECR9 (CPG_BASE + 0x0BA4U)
83/* Secure Software Reset Access Enable Control Register 10 */
84#define SCSRSTECR10 (CPG_BASE + 0x0BA8U)
85/* Secure Software Reset Access Enable Control Register 11 */
86#define SCSRSTECR11 (CPG_BASE + 0x0BACU)
87
88/* CPG (REALTIME) registers */
89
90/* Realtime Module Stop Control Register 0 */
91#define RMSTPCR0 (CPG_BASE + 0x0110U)
92/* Realtime Module Stop Control Register 1 */
93#define RMSTPCR1 (CPG_BASE + 0x0114U)
94/* Realtime Module Stop Control Register 2 */
95#define RMSTPCR2 (CPG_BASE + 0x0118U)
96/* Realtime Module Stop Control Register 3 */
97#define RMSTPCR3 (CPG_BASE + 0x011CU)
98/* Realtime Module Stop Control Register 4 */
99#define RMSTPCR4 (CPG_BASE + 0x0120U)
100/* Realtime Module Stop Control Register 5 */
101#define RMSTPCR5 (CPG_BASE + 0x0124U)
102/* Realtime Module Stop Control Register 6 */
103#define RMSTPCR6 (CPG_BASE + 0x0128U)
104/* Realtime Module Stop Control Register 7 */
105#define RMSTPCR7 (CPG_BASE + 0x012CU)
106/* Realtime Module Stop Control Register 8 */
107#define RMSTPCR8 (CPG_BASE + 0x0980U)
108/* Realtime Module Stop Control Register 9 */
109#define RMSTPCR9 (CPG_BASE + 0x0984U)
110/* Realtime Module Stop Control Register 10 */
111#define RMSTPCR10 (CPG_BASE + 0x0988U)
112/* Realtime Module Stop Control Register 11 */
113#define RMSTPCR11 (CPG_BASE + 0x098CU)
114
115/* CPG (SYSTEM) registers */
116
117/* System Module Stop Control Register 0 */
118#define SMSTPCR0 (CPG_BASE + 0x0130U)
119/* System Module Stop Control Register 1 */
120#define SMSTPCR1 (CPG_BASE + 0x0134U)
121/* System Module Stop Control Register 2 */
122#define SMSTPCR2 (CPG_BASE + 0x0138U)
123/* System Module Stop Control Register 3 */
124#define SMSTPCR3 (CPG_BASE + 0x013CU)
125/* System Module Stop Control Register 4 */
126#define SMSTPCR4 (CPG_BASE + 0x0140U)
127/* System Module Stop Control Register 5 */
128#define SMSTPCR5 (CPG_BASE + 0x0144U)
129/* System Module Stop Control Register 6 */
130#define SMSTPCR6 (CPG_BASE + 0x0148U)
131/* System Module Stop Control Register 7 */
132#define SMSTPCR7 (CPG_BASE + 0x014CU)
133/* System Module Stop Control Register 8 */
134#define SMSTPCR8 (CPG_BASE + 0x0990U)
135/* System Module Stop Control Register 9 */
136#define SMSTPCR9 (CPG_BASE + 0x0994U)
137/* System Module Stop Control Register 10 */
138#define SMSTPCR10 (CPG_BASE + 0x0998U)
139/* System Module Stop Control Register 11 */
140#define SMSTPCR11 (CPG_BASE + 0x099CU)
141
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000142#endif /* CPG_REGISTERS_H */