blob: b6fc29bbdded6b423b3facee07d585ff576c2cfe [file] [log] [blame]
developer3f3f1ab2019-05-02 22:26:22 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef MT_GIC_V3_H
8#define MT_GIC_V3_H
9
10#include <lib/mmio.h>
11
developer3f3f1ab2019-05-02 22:26:22 +080012#define GIC_INT_MASK (MCUCFG_BASE + 0x5e8)
13#define GIC500_ACTIVE_SEL_SHIFT 3
14#define GIC500_ACTIVE_SEL_MASK (0x7 << GIC500_ACTIVE_SEL_SHIFT)
15#define GIC500_ACTIVE_CPU_SHIFT 16
16#define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT)
17
developere2f13322019-10-04 10:47:11 +080018#define NR_INT_POL_CTL 20
19
developer3f3f1ab2019-05-02 22:26:22 +080020void mt_gic_driver_init(void);
21void mt_gic_init(void);
22void mt_gic_set_pending(uint32_t irq);
23uint32_t mt_gic_get_pending(uint32_t irq);
24void mt_gic_cpuif_enable(void);
25void mt_gic_cpuif_disable(void);
developere2f13322019-10-04 10:47:11 +080026void mt_gic_rdistif_init(void);
27void mt_gic_distif_save(void);
28void mt_gic_distif_restore(void);
29void mt_gic_rdistif_save(void);
30void mt_gic_rdistif_restore(void);
developer3f3f1ab2019-05-02 22:26:22 +080031void mt_gic_sync_dcm_enable(void);
32void mt_gic_sync_dcm_disable(void);
33
34#endif /* MT_GIC_V3_H */