| Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <cpu_macros.S> |
| 9 | #include <css_def.h> |
| 10 | |
| 11 | .weak plat_secondary_cold_boot_setup |
| 12 | .weak plat_get_my_entrypoint |
| 13 | .globl css_calc_core_pos_swap_cluster |
| 14 | .weak plat_is_my_cpu_primary |
| 15 | |
| 16 | /* --------------------------------------------------------------------- |
| 17 | * void plat_secondary_cold_boot_setup(void); |
| 18 | * In the normal boot flow, cold-booting secondary |
| 19 | * CPUs is not yet implemented and they panic. |
| 20 | * --------------------------------------------------------------------- |
| 21 | */ |
| 22 | func plat_secondary_cold_boot_setup |
| 23 | /* TODO: Implement secondary CPU cold boot setup on CSS platforms */ |
| 24 | cb_panic: |
| 25 | b cb_panic |
| 26 | endfunc plat_secondary_cold_boot_setup |
| 27 | |
| 28 | /* --------------------------------------------------------------------- |
| 29 | * uintptr_t plat_get_my_entrypoint (void); |
| 30 | * |
| 31 | * Main job of this routine is to distinguish between a cold and a warm |
| 32 | * boot. On CSS platforms, this distinction is based on the contents of |
| 33 | * the Trusted Mailbox. It is initialised to zero by the SCP before the |
| 34 | * AP cores are released from reset. Therefore, a zero mailbox means |
| 35 | * it's a cold reset. |
| 36 | * |
| 37 | * This functions returns the contents of the mailbox, i.e.: |
| 38 | * - 0 for a cold boot; |
| 39 | * - the warm boot entrypoint for a warm boot. |
| 40 | * --------------------------------------------------------------------- |
| 41 | */ |
| 42 | func plat_get_my_entrypoint |
| 43 | ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE |
| 44 | ldr r0, [r0] |
| 45 | bx lr |
| 46 | endfunc plat_get_my_entrypoint |
| 47 | |
| 48 | /* ----------------------------------------------------------- |
| 49 | * unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr) |
| 50 | * Utility function to calculate the core position by |
| 51 | * swapping the cluster order. This is necessary in order to |
| 52 | * match the format of the boot information passed by the SCP |
| 53 | * and read in plat_is_my_cpu_primary below. |
| 54 | * ----------------------------------------------------------- |
| 55 | */ |
| 56 | func css_calc_core_pos_swap_cluster |
| 57 | and r1, r0, #MPIDR_CPU_MASK |
| 58 | and r0, r0, #MPIDR_CLUSTER_MASK |
| 59 | eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order |
| 60 | add r0, r1, r0, LSR #6 |
| 61 | bx lr |
| 62 | endfunc css_calc_core_pos_swap_cluster |
| 63 | |
| 64 | /* ----------------------------------------------------- |
| 65 | * unsigned int plat_is_my_cpu_primary (void); |
| 66 | * |
| 67 | * Find out whether the current cpu is the primary |
| 68 | * cpu (applicable ony after a cold boot) |
| 69 | * ----------------------------------------------------- |
| 70 | */ |
| 71 | func plat_is_my_cpu_primary |
| 72 | mov r10, lr |
| 73 | bl plat_my_core_pos |
| 74 | ldr r1, =SCP_BOOT_CFG_ADDR |
| 75 | ldr r1, [r1] |
| 76 | ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ |
| 77 | #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH |
| 78 | cmp r0, r1 |
| 79 | moveq r0, #1 |
| 80 | movne r0, #0 |
| 81 | bx r10 |
| 82 | endfunc plat_is_my_cpu_primary |