Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <string.h> |
| 9 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 10 | #include <arch.h> |
| 11 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 14 | #include <context.h> |
Harvey Hsieh | fbdfce1 | 2016-11-23 19:13:08 +0800 | [diff] [blame] | 15 | #include <cortex_a57.h> |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 16 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <lib/el3_runtime/context_mgmt.h> |
| 18 | #include <lib/psci/psci.h> |
| 19 | #include <plat/common/platform.h> |
| 20 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 21 | #include <mce.h> |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 22 | #include <smmu.h> |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 23 | #include <stdbool.h> |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 24 | #include <t18x_ari.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 25 | #include <tegra_private.h> |
| 26 | |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 27 | extern void memcpy16(void *dest, const void *src, unsigned int length); |
| 28 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 29 | extern void prepare_cpu_pwr_dwn(void); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 30 | extern void tegra186_cpu_reset_handler(void); |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 31 | extern uint32_t __tegra186_cpu_reset_handler_end, |
| 32 | __tegra186_smmu_context; |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 33 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 34 | /* TZDRAM offset for saving SMMU context */ |
| 35 | #define TEGRA186_SMMU_CTX_OFFSET 16UL |
| 36 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 37 | /* state id mask */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 38 | #define TEGRA186_STATE_ID_MASK 0xFU |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 39 | /* constants to get power state's wake time */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 40 | #define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0U |
| 41 | #define TEGRA186_WAKE_TIME_SHIFT 4U |
Varun Wadekar | 698e7c6 | 2016-03-28 15:05:03 -0700 | [diff] [blame] | 42 | /* default core wake mask for CPU_SUSPEND */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 43 | #define TEGRA186_CORE_WAKE_MASK 0x180cU |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 44 | /* context size to save during system suspend */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 45 | #define TEGRA186_SE_CONTEXT_SIZE 3U |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 46 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 47 | static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 48 | static struct tegra_psci_percpu_data { |
| 49 | uint32_t wake_time; |
| 50 | } __aligned(CACHE_WRITEBACK_GRANULE) tegra_percpu_data[PLATFORM_CORE_COUNT]; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 51 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 52 | int32_t tegra_soc_validate_power_state(uint32_t power_state, |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 53 | psci_power_state_t *req_state) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 54 | { |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 55 | uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; |
| 56 | uint32_t cpu = plat_my_core_pos(); |
| 57 | int32_t ret = PSCI_E_SUCCESS; |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 58 | |
Krishna Sitaraman | 86569d1 | 2016-08-18 15:41:21 -0700 | [diff] [blame] | 59 | /* save the core wake time (in TSC ticks)*/ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 60 | tegra_percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) |
Krishna Sitaraman | 86569d1 | 2016-08-18 15:41:21 -0700 | [diff] [blame] | 61 | << TEGRA186_WAKE_TIME_SHIFT; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 62 | |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 63 | /* |
| 64 | * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that |
| 65 | * the correct value is read in tegra_soc_pwr_domain_suspend(), which |
| 66 | * is called with caches disabled. It is possible to read a stale value |
| 67 | * from DRAM in that function, because the L2 cache is not flushed |
| 68 | * unless the cluster is entering CC6/CC7. |
| 69 | */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 70 | clean_dcache_range((uint64_t)&tegra_percpu_data[cpu], |
| 71 | sizeof(tegra_percpu_data[cpu])); |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 72 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 73 | /* Sanity check the requested state id */ |
| 74 | switch (state_id) { |
| 75 | case PSTATE_ID_CORE_IDLE: |
| 76 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 77 | |
| 78 | /* Core powerdown request */ |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 79 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 80 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 81 | |
| 82 | break; |
| 83 | |
| 84 | default: |
| 85 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 86 | ret = PSCI_E_INVALID_PARAMS; |
| 87 | break; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 88 | } |
| 89 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 90 | return ret; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 91 | } |
| 92 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 93 | int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 94 | { |
| 95 | const plat_local_state_t *pwr_domain_state; |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 96 | uint8_t stateid_afflvl0, stateid_afflvl2; |
| 97 | uint32_t cpu = plat_my_core_pos(); |
| 98 | const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 99 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 100 | uint64_t smmu_ctx_base; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 101 | uint32_t val; |
| 102 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 103 | /* get the state ID */ |
| 104 | pwr_domain_state = target_state->pwr_domain_state; |
| 105 | stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & |
| 106 | TEGRA186_STATE_ID_MASK; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 107 | stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
| 108 | TEGRA186_STATE_ID_MASK; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 109 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 110 | if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || |
| 111 | (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 112 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 113 | /* Enter CPU idle/powerdown */ |
| 114 | val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? |
| 115 | TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 116 | (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, |
| 117 | tegra_percpu_data[cpu].wake_time, 0U); |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 118 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 119 | } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 120 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 121 | /* save SE registers */ |
| 122 | se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + |
| 123 | SE_MUTEX_WATCHDOG_NS_LIMIT); |
| 124 | se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + |
| 125 | RNG_MUTEX_WATCHDOG_NS_LIMIT); |
| 126 | se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + |
| 127 | PKA_MUTEX_WATCHDOG_NS_LIMIT); |
| 128 | |
| 129 | /* save 'Secure Boot' Processor Feature Config Register */ |
| 130 | val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); |
| 131 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); |
| 132 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 133 | /* save SMMU context to TZDRAM */ |
| 134 | smmu_ctx_base = params_from_bl2->tzdram_base + |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 135 | ((uintptr_t)&__tegra186_smmu_context - |
| 136 | (uintptr_t)tegra186_cpu_reset_handler); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 137 | tegra_smmu_save_context((uintptr_t)smmu_ctx_base); |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 138 | |
| 139 | /* Prepare for system suspend */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 140 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 141 | cstate_info.system = TEGRA_ARI_SYSTEM_SC7; |
| 142 | cstate_info.system_state_force = 1; |
| 143 | cstate_info.update_wake_mask = 1; |
| 144 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 145 | /* Loop until system suspend is allowed */ |
| 146 | do { |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 147 | val = (uint32_t)mce_command_handler( |
| 148 | (uint64_t)MCE_CMD_IS_SC7_ALLOWED, |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 149 | TEGRA_ARI_CORE_C7, |
| 150 | MCE_CORE_SLEEP_TIME_INFINITE, |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 151 | 0U); |
| 152 | } while (val == 0U); |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 153 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 154 | /* Instruct the MCE to enter system suspend state */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 155 | (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, |
| 156 | TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); |
| 157 | } else { |
| 158 | ; /* do nothing */ |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | return PSCI_E_SUCCESS; |
| 162 | } |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 163 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 164 | /******************************************************************************* |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 165 | * Helper function to check if this is the last ON CPU in the cluster |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 166 | ******************************************************************************/ |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 167 | static bool tegra_last_cpu_in_cluster(const plat_local_state_t *states, |
| 168 | uint32_t ncpu) |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 169 | { |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 170 | plat_local_state_t target; |
| 171 | bool last_on_cpu = true; |
| 172 | uint32_t num_cpus = ncpu, pos = 0; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 173 | |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 174 | do { |
| 175 | target = states[pos]; |
| 176 | if (target != PLAT_MAX_OFF_STATE) { |
| 177 | last_on_cpu = false; |
| 178 | } |
| 179 | --num_cpus; |
| 180 | pos++; |
| 181 | } while (num_cpus != 0U); |
| 182 | |
| 183 | return last_on_cpu; |
| 184 | } |
| 185 | |
| 186 | /******************************************************************************* |
| 187 | * Helper function to get target power state for the cluster |
| 188 | ******************************************************************************/ |
| 189 | static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, |
| 190 | uint32_t ncpu) |
| 191 | { |
| 192 | uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK; |
| 193 | uint32_t cpu = plat_my_core_pos(); |
| 194 | int32_t ret; |
| 195 | plat_local_state_t target = states[core_pos]; |
| 196 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 197 | |
| 198 | /* CPU suspend */ |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 199 | if (target == PSTATE_ID_CORE_POWERDN) { |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 200 | |
| 201 | /* Program default wake mask */ |
| 202 | cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK; |
| 203 | cstate_info.update_wake_mask = 1; |
| 204 | mce_update_cstate_info(&cstate_info); |
| 205 | |
| 206 | /* Check if CCx state is allowed. */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 207 | ret = mce_command_handler((uint64_t)MCE_CMD_IS_CCX_ALLOWED, |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 208 | (uint64_t)TEGRA_ARI_CORE_C7, |
| 209 | tegra_percpu_data[cpu].wake_time, |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 210 | 0U); |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 211 | if (ret == 0) { |
| 212 | target = PSCI_LOCAL_STATE_RUN; |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 213 | } |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | /* CPU off */ |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 217 | if (target == PLAT_MAX_OFF_STATE) { |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 218 | |
| 219 | /* Enable cluster powerdn from last CPU in the cluster */ |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 220 | if (tegra_last_cpu_in_cluster(states, ncpu)) { |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 221 | |
| 222 | /* Enable CC7 state and turn off wake mask */ |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 223 | cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 224 | cstate_info.update_wake_mask = 1; |
| 225 | mce_update_cstate_info(&cstate_info); |
| 226 | |
| 227 | /* Check if CCx state is allowed. */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 228 | ret = mce_command_handler((uint64_t)MCE_CMD_IS_CCX_ALLOWED, |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 229 | (uint64_t)TEGRA_ARI_CORE_C7, |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 230 | MCE_CORE_SLEEP_TIME_INFINITE, |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 231 | 0U); |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 232 | if (ret == 0) { |
| 233 | target = PSCI_LOCAL_STATE_RUN; |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 234 | } |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 235 | |
| 236 | } else { |
| 237 | |
| 238 | /* Turn off wake_mask */ |
| 239 | cstate_info.update_wake_mask = 1; |
| 240 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 241 | target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 242 | } |
| 243 | } |
| 244 | |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 245 | return target; |
| 246 | } |
| 247 | |
| 248 | /******************************************************************************* |
| 249 | * Platform handler to calculate the proper target power level at the |
| 250 | * specified affinity level |
| 251 | ******************************************************************************/ |
| 252 | plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, |
| 253 | const plat_local_state_t *states, |
| 254 | uint32_t ncpu) |
| 255 | { |
| 256 | plat_local_state_t target = PSCI_LOCAL_STATE_RUN; |
| 257 | int cpu = plat_my_core_pos(); |
| 258 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 259 | /* System Suspend */ |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 260 | if ((lvl == (uint32_t)MPIDR_AFFLVL2) && |
| 261 | (states[cpu] == PSTATE_ID_SOC_POWERDN)) { |
| 262 | target = PSTATE_ID_SOC_POWERDN; |
| 263 | } |
| 264 | |
| 265 | /* CPU off, CPU suspend */ |
| 266 | if (lvl == (uint32_t)MPIDR_AFFLVL1) { |
| 267 | target = tegra_get_afflvl1_pwr_state(states, ncpu); |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 268 | } |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 269 | |
Varun Wadekar | 1e7250b | 2017-05-24 08:47:15 -0700 | [diff] [blame] | 270 | /* target cluster/system state */ |
| 271 | return target; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 272 | } |
| 273 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 274 | int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 275 | { |
| 276 | const plat_local_state_t *pwr_domain_state = |
| 277 | target_state->pwr_domain_state; |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 278 | const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 279 | uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 280 | TEGRA186_STATE_ID_MASK; |
Steven Kao | 235e9c3 | 2016-12-23 15:43:17 +0800 | [diff] [blame] | 281 | uint64_t val; |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 282 | |
| 283 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 284 | /* |
| 285 | * The TZRAM loses power when we enter system suspend. To |
| 286 | * allow graceful exit from system suspend, we need to copy |
| 287 | * BL3-1 over to TZDRAM. |
| 288 | */ |
| 289 | val = params_from_bl2->tzdram_base + |
| 290 | ((uintptr_t)&__tegra186_cpu_reset_handler_end - |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 291 | (uintptr_t)&tegra186_cpu_reset_handler); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 292 | memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, |
| 293 | (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); |
| 294 | } |
| 295 | |
| 296 | return PSCI_E_SUCCESS; |
| 297 | } |
| 298 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 299 | int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 300 | { |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 301 | uint32_t target_cpu = mpidr & (uint64_t)MPIDR_CPU_MASK; |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 302 | uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 303 | (uint64_t)MPIDR_AFFINITY_BITS; |
| 304 | int32_t ret = PSCI_E_SUCCESS; |
| 305 | |
| 306 | if (target_cluster > (uint64_t)MPIDR_AFFLVL1) { |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 307 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 308 | ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 309 | ret = PSCI_E_NOT_PRESENT; |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 310 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 311 | } else { |
| 312 | /* construct the target CPU # */ |
| 313 | target_cpu |= (target_cluster << 2); |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 314 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 315 | (void)mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); |
| 316 | } |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 317 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 318 | return ret; |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 319 | } |
| 320 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 321 | int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 322 | { |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 323 | uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; |
| 324 | uint8_t stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 325 | mce_cstate_info_t cstate_info = { 0 }; |
Harvey Hsieh | fbdfce1 | 2016-11-23 19:13:08 +0800 | [diff] [blame] | 326 | uint64_t impl, val; |
| 327 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
| 328 | |
| 329 | impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; |
| 330 | |
| 331 | /* |
| 332 | * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186 |
| 333 | * A02p and beyond). |
| 334 | */ |
| 335 | if ((plat_params->l2_ecc_parity_prot_dis != 1) && |
| 336 | (impl != (uint64_t)DENVER_IMPL)) { |
| 337 | |
| 338 | val = read_l2ctlr_el1(); |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 339 | val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; |
Harvey Hsieh | fbdfce1 | 2016-11-23 19:13:08 +0800 | [diff] [blame] | 340 | write_l2ctlr_el1(val); |
| 341 | } |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 342 | |
| 343 | /* |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 344 | * Reset power state info for CPUs when onlining, we set |
| 345 | * deepest power when offlining a core but that may not be |
| 346 | * requested by non-secure sw which controls idle states. It |
| 347 | * will re-init this info from non-secure software when the |
| 348 | * core come online. |
Varun Wadekar | d2da47a | 2016-04-09 00:40:45 -0700 | [diff] [blame] | 349 | */ |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 350 | if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) { |
| 351 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 352 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1; |
| 353 | cstate_info.update_wake_mask = 1; |
| 354 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 355 | } |
Varun Wadekar | d2da47a | 2016-04-09 00:40:45 -0700 | [diff] [blame] | 356 | |
| 357 | /* |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 358 | * Check if we are exiting from deep sleep and restore SE |
| 359 | * context if we are. |
| 360 | */ |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 361 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 362 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 363 | mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, |
| 364 | se_regs[0]); |
| 365 | mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, |
| 366 | se_regs[1]); |
| 367 | mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, |
| 368 | se_regs[2]); |
| 369 | |
| 370 | /* Init SMMU */ |
| 371 | tegra_smmu_init(); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 372 | |
| 373 | /* |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 374 | * Reset power state info for the last core doing SC7 |
| 375 | * entry and exit, we set deepest power state as CC7 |
| 376 | * and SC7 for SC7 entry which may not be requested by |
| 377 | * non-secure SW which controls idle states. |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 378 | */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 379 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 380 | cstate_info.system = TEGRA_ARI_SYSTEM_SC1; |
| 381 | cstate_info.update_wake_mask = 1; |
| 382 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 383 | } |
| 384 | |
| 385 | return PSCI_E_SUCCESS; |
| 386 | } |
| 387 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 388 | int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 389 | { |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 390 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; |
| 391 | |
| 392 | (void)target_state; |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 393 | |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 394 | /* Disable Denver's DCO operations */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 395 | if (impl == DENVER_IMPL) { |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 396 | denver_disable_dco(); |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 397 | } |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 398 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 399 | /* Turn off CPU */ |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 400 | (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, |
| 401 | MCE_CORE_SLEEP_TIME_INFINITE, 0U); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 402 | |
| 403 | return PSCI_E_SUCCESS; |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 404 | } |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 405 | |
| 406 | __dead2 void tegra_soc_prepare_system_off(void) |
| 407 | { |
Varun Wadekar | 71d0e8d | 2017-05-17 14:35:33 -0700 | [diff] [blame] | 408 | /* power off the entire system */ |
| 409 | mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF); |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 410 | |
| 411 | wfi(); |
| 412 | |
| 413 | /* wait for the system to power down */ |
| 414 | for (;;) { |
| 415 | ; |
| 416 | } |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 417 | } |
Varun Wadekar | 38020c9 | 2016-01-07 14:36:12 -0800 | [diff] [blame] | 418 | |
Anthony Zhou | 5d1bb05 | 2017-03-03 16:23:08 +0800 | [diff] [blame] | 419 | int32_t tegra_soc_prepare_system_reset(void) |
Varun Wadekar | 38020c9 | 2016-01-07 14:36:12 -0800 | [diff] [blame] | 420 | { |
| 421 | mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); |
| 422 | |
| 423 | return PSCI_E_SUCCESS; |
| 424 | } |