Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 1 | Arm Development Platform Build Options |
| 2 | ====================================== |
| 3 | |
| 4 | Arm Platform Build Options |
| 5 | -------------------------- |
| 6 | |
| 7 | - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured |
| 8 | DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load |
| 9 | BL31 in TZC secured DRAM. If TSP is present, then setting this option also |
| 10 | sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build |
| 11 | flag. |
| 12 | |
| 13 | - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>`` |
| 14 | frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The |
| 15 | frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which |
| 16 | should match the frame used by the Non-Secure image (normally the Linux |
| 17 | kernel). Default is true (access to the frame is allowed). |
| 18 | |
| 19 | - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog. |
| 20 | By default, Arm platforms use a watchdog to trigger a system reset in case |
| 21 | an error is encountered during the boot process (for example, when an image |
| 22 | could not be loaded or authenticated). The watchdog is enabled in the early |
| 23 | platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The |
| 24 | Trusted Watchdog may be disabled at build time for testing or development |
| 25 | purposes. |
| 26 | |
| 27 | - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to |
| 28 | have specific values at boot. This boolean option allows the Trusted Firmware |
| 29 | to have a Linux kernel image as BL33 by preparing the registers to these |
| 30 | values before jumping to BL33. This option defaults to 0 (disabled). For |
| 31 | AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when |
| 32 | using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set |
| 33 | to the location of a device tree blob (DTB) already loaded in memory. The |
| 34 | Linux Image address must be specified using the ``PRELOADED_BL33_BASE`` |
| 35 | option. |
| 36 | |
| 37 | - ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to |
| 38 | cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag |
| 39 | is set, the functions which deal with MPIDR assume that the ``MT`` bit in |
| 40 | MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of |
| 41 | this flag is 0. Note that this option is not used on FVP platforms. |
| 42 | |
| 43 | - ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding |
| 44 | for the construction of composite state-ID in the power-state parameter. |
| 45 | The existing PSCI clients currently do not support this encoding of |
| 46 | State-ID yet. Hence this flag is used to configure whether to use the |
| 47 | recommended State-ID encoding or not. The default value of this flag is 0, |
| 48 | in which case the platform is configured to expect NULL in the State-ID |
| 49 | field of power-state parameter. |
| 50 | |
| 51 | - ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the |
| 52 | location of the ROTPK hash returned by the function ``plat_get_rotpk_info()`` |
| 53 | for Arm platforms. Depending on the selected option, the proper private key |
| 54 | must be specified using the ``ROT_KEY`` option when building the Trusted |
| 55 | Firmware. This private key will be used by the certificate generation tool |
| 56 | to sign the BL2 and Trusted Key certificates. Available options for |
| 57 | ``ARM_ROTPK_LOCATION`` are: |
| 58 | |
| 59 | - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 60 | registers. |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 61 | - ``devel_rsa`` : return a development public key hash embedded in the BL1 |
| 62 | and BL2 binaries. This hash has been obtained from the RSA public key |
| 63 | ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use |
| 64 | this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` |
| 65 | when creating the certificates. |
| 66 | - ``devel_ecdsa`` : return a development public key hash embedded in the BL1 |
| 67 | and BL2 binaries. This hash has been obtained from the ECDSA public key |
| 68 | ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To |
| 69 | use this option, ``arm_rotprivk_ecdsa.pem`` must be specified as |
| 70 | ``ROT_KEY`` when creating the certificates. |
| 71 | |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 72 | - ``ARM_ROTPK_HASH``: used when ``ARM_ROTPK_LOCATION=devel_*``. Specifies the |
| 73 | location of the ROTPK hash. Not expected to be a build option. This defaults to |
| 74 | ``plat/arm/board/common/rotpk/*_sha256.bin`` depending on the specified algorithm. |
| 75 | Providing ``ROT_KEY`` enforces generation of the hash from the ``ROT_KEY`` and |
| 76 | overwrites the default hash file. |
| 77 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 78 | - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options: |
| 79 | |
| 80 | - ``tsram`` : Trusted SRAM (default option when TBB is not enabled) |
| 81 | - ``tdram`` : Trusted DRAM (if available) |
| 82 | - ``dram`` : Secure region in DRAM (default option when TBB is enabled, |
| 83 | configured by the TrustZone controller) |
| 84 | |
| 85 | - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1 |
| 86 | of the translation tables library instead of version 2. It is set to 0 by |
| 87 | default, which selects version 2. |
| 88 | |
| 89 | - ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke ArmĀ® |
| 90 | TrustZoneĀ® CryptoCell functionality for Trusted Board Boot on capable Arm |
| 91 | platforms. If this option is specified, then the path to the CryptoCell |
| 92 | SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. |
| 93 | |
Olivier Deprez | bcaa068 | 2020-04-01 21:28:26 +0200 | [diff] [blame] | 94 | - ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the |
| 95 | SPMC Core manifest. Valid when ``SPD=spmd`` is selected. |
| 96 | |
Arunachalam Ganapathy | 47d514d | 2020-12-08 16:35:18 +0000 | [diff] [blame] | 97 | - ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in tb_fw_config |
| 98 | device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest |
| 99 | file name contains pattern optee_sp. |
| 100 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 101 | For a better understanding of these options, the Arm development platform memory |
| 102 | map is explained in the :ref:`Firmware Design`. |
| 103 | |
| 104 | .. _build_options_arm_css_platform: |
| 105 | |
| 106 | Arm CSS Platform-Specific Build Options |
| 107 | --------------------------------------- |
| 108 | |
| 109 | - ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version |
| 110 | incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards |
| 111 | compatible change to the MTL protocol, used for AP/SCP communication. |
| 112 | TF-A no longer supports earlier SCP versions. If this option is set to 1 |
| 113 | then TF-A will detect if an earlier version is in use. Default is 1. |
| 114 | |
| 115 | - ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and |
| 116 | SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded |
| 117 | during boot. Default is 1. |
| 118 | |
| 119 | - ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers |
| 120 | instead of SCPI/BOM driver for communicating with the SCP during power |
| 121 | management operations and for SCP RAM Firmware transfer. If this option |
| 122 | is set to 1, then SCMI/SDS drivers will be used. Default is 0. |
| 123 | |
Vijayenthiran Subramaniam | bc48991 | 2019-12-26 17:45:58 +0530 | [diff] [blame] | 124 | - ``CSS_SGI_CHIP_COUNT``: Configures the number of chips on a SGI/RD platform |
| 125 | which supports multi-chip operation. If ``CSS_SGI_CHIP_COUNT`` is set to any |
| 126 | valid value greater than 1, the platform code performs required configuration |
| 127 | to support multi-chip operation. |
| 128 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 129 | -------------- |
| 130 | |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 131 | *Copyright (c) 2019-2020, Arm Limited. All rights reserved.* |