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git01.mediatek.com / filogic / atf / 59400a481a6a21919f39a4d46359c9b362072065 / . / plat / intel / soc / stratix10 / platform_def.h
blob: 88469eda9f7ae5f70deb6afd5873f90eb62ddc3a [file] [log] [blame]
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame^]1/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <arch.h>
11#include <common/bl_common.h>
12#include <common/interrupt_props.h>
13#include <common/tbbr/tbbr_img_def.h>
14#include <drivers/arm/gic_common.h>
15#include <plat/common/common_def.h>
16
17
18/* Define next boot image name and offset */
19#define PLAT_NS_IMAGE_OFFSET 0x50000
20#define PLAT_HANDOFF_OFFSET 0xFFE3F000
21
22/*******************************************************************************
23 * Platform binary types for linking
24 ******************************************************************************/
25#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
26#define PLATFORM_LINKER_ARCH aarch64
27
28/* Stratix 10 supports up to 124GB RAM */
29#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
30#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
31
32
33/*******************************************************************************
34 * Generic platform constants
35 ******************************************************************************/
36#define PLAT_PRIMARY_CPU 0
37#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0
38
39/* Size of cacheable stacks */
40#define PLATFORM_STACK_SIZE 0x2000
41
42/* PSCI related constant */
43#define PLAT_NUM_POWER_DOMAINS 5
44#define PLAT_MAX_PWR_LVL 1
45#define PLAT_MAX_RET_STATE 1
46#define PLAT_MAX_OFF_STATE 2
47#define PLATFORM_SYSTEM_COUNT 1
48#define PLATFORM_CLUSTER_COUNT 1
49#define PLATFORM_CLUSTER0_CORE_COUNT 4
50#define PLATFORM_CLUSTER1_CORE_COUNT 0
51#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
52 PLATFORM_CLUSTER0_CORE_COUNT)
53#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
54
55/* Interrupt related constant */
56
57#define INTEL_S10_IRQ_SEC_PHY_TIMER 29
58
59#define INTEL_S10_IRQ_SEC_SGI_0 8
60#define INTEL_S10_IRQ_SEC_SGI_1 9
61#define INTEL_S10_IRQ_SEC_SGI_2 10
62#define INTEL_S10_IRQ_SEC_SGI_3 11
63#define INTEL_S10_IRQ_SEC_SGI_4 12
64#define INTEL_S10_IRQ_SEC_SGI_5 13
65#define INTEL_S10_IRQ_SEC_SGI_6 14
66#define INTEL_S10_IRQ_SEC_SGI_7 15
67
68#define TSP_IRQ_SEC_PHY_TIMER INTEL_S10_IRQ_SEC_PHY_TIMER
69#define TSP_SEC_MEM_BASE BL32_BASE
70#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
71/*******************************************************************************
72 * Platform memory map related constants
73 ******************************************************************************/
74#define DRAM_BASE (0x0)
75#define DRAM_SIZE (0x80000000)
76
77#define OCRAM_BASE (0xFFE00000)
78#define OCRAM_SIZE (0x00100000)
79
80#define MEM64_BASE (0x0100000000)
81#define MEM64_SIZE (0x1F00000000)
82
83#define DEVICE1_BASE (0x80000000)
84#define DEVICE1_SIZE (0x60000000)
85
86#define DEVICE2_BASE (0xF7000000)
87#define DEVICE2_SIZE (0x08E00000)
88
89#define DEVICE3_BASE (0xFFFC0000)
90#define DEVICE3_SIZE (0x00008000)
91
92#define DEVICE4_BASE (0x2000000000)
93#define DEVICE4_SIZE (0x0100000000)
94
95/*******************************************************************************
96 * BL31 specific defines.
97 ******************************************************************************/
98/*
99 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
100 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
101 * little space for growth.
102 */
103
104
105#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
106
107#define BL1_RO_BASE (0xffe00000)
108#define BL1_RO_LIMIT (0xffe0f000)
109#define BL1_RW_BASE (0xffe10000)
110#define BL1_RW_LIMIT (0xffe1ffff)
111#define BL1_RW_SIZE (0x14000)
112
113#define BL2_BASE (0xffe00000)
114#define BL2_LIMIT (0xffe1c000)
115
116#define BL31_BASE (0xffe1c000)
117#define BL31_LIMIT (0xffe3ffff)
118
119/*******************************************************************************
120 * Platform specific page table and MMU setup constants
121 ******************************************************************************/
122#define MAX_XLAT_TABLES 8
123#define MAX_MMAP_REGIONS 16
124
125/*******************************************************************************
126 * Declarations and constants to access the mailboxes safely. Each mailbox is
127 * aligned on the biggest cache line size in the platform. This is known only
128 * to the platform as it might have a combination of integrated and external
129 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
130 * line at any cache level. They could belong to different cpus/clusters &
131 * get written while being protected by different locks causing corruption of
132 * a valid mailbox address.
133 ******************************************************************************/
134#define CACHE_WRITEBACK_SHIFT 6
135#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
136
137#define PLAT_GIC_BASE (0xFFFC0000)
138#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
139#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
140#define PLAT_GICR_BASE 0
141
142/*******************************************************************************
143 * UART related constants
144 ******************************************************************************/
145#define PLAT_UART0_BASE (0xFFC02000)
146#define PLAT_UART1_BASE (0xFFC02100)
147
148#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
149
150#define PLAT_BAUDRATE (115200)
151#define PLAT_UART_CLOCK (100000000)
152
153/*******************************************************************************
154 * System counter frequency related constants
155 ******************************************************************************/
156#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
157#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
158
159#define PLAT_INTEL_S10_GICD_BASE PLAT_GICD_BASE
160#define PLAT_INTEL_S10_GICC_BASE PLAT_GICC_BASE
161
162/*
163 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
164 * terminology. On a GICv2 system or mode, the lists will be merged and treated
165 * as Group 0 interrupts.
166 */
167#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \
168 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
169 grp, GIC_INTR_CFG_LEVEL), \
170 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
171 GIC_INTR_CFG_EDGE), \
172 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
173 GIC_INTR_CFG_EDGE), \
174 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
175 GIC_INTR_CFG_EDGE), \
176 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
177 GIC_INTR_CFG_EDGE), \
178 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
179 GIC_INTR_CFG_EDGE), \
180 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
181 GIC_INTR_CFG_EDGE), \
182 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
183 GIC_INTR_CFG_EDGE), \
184 INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
185 GIC_INTR_CFG_EDGE)
186
187#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp)
188
189#define MAX_IO_HANDLES 4
190#define MAX_IO_DEVICES 4
191#define MAX_IO_BLOCK_DEVICES 2
192
193
194#endif /* __PLATFORM_DEF_H__ */
195