blob: 97b2a19390f5c1bef25d8e091c95f1660c78237b [file] [log] [blame]
Pankaj Gupta1f9eab72020-12-09 14:02:39 +05301/*
2 * Copyright 2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#include <assert.h>
9
10#include <common/debug.h>
11#include <lib/mmio.h>
12#include <lib/xlat_tables/xlat_tables_v2.h>
13#include <qspi.h>
14
15int qspi_io_setup(uintptr_t nxp_qspi_flash_addr,
16 size_t nxp_qspi_flash_size,
17 uintptr_t fip_offset)
18{
19 uint32_t qspi_mcr_val = qspi_in32(CHS_QSPI_MCR);
20
21 /* Enable and change endianness of QSPI IP */
22 qspi_out32(CHS_QSPI_MCR, (qspi_mcr_val | CHS_QSPI_64LE));
23
24 /* Adding QSPI Memory Map in XLAT Table */
25 mmap_add_region(nxp_qspi_flash_addr, nxp_qspi_flash_addr,
26 nxp_qspi_flash_size, MT_MEMORY | MT_RW);
27
28 return 0;
29}