developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <drivers/arm/gic_common.h> |
| 12 | |
| 13 | #define PLAT_PRIMARY_CPU 0x0 |
| 14 | |
| 15 | #define IO_PHYS 0x10000000 |
| 16 | #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) |
| 17 | #define PERI_BASE (IO_PHYS + 0x3000) |
| 18 | #define GPIO_BASE (IO_PHYS + 0x5000) |
| 19 | #define SPM_BASE (IO_PHYS + 0x6000) |
| 20 | #define SLEEP_REG_MD_BASE (IO_PHYS + 0xf000) |
| 21 | #define RGU_BASE (IO_PHYS + 0x7000) |
| 22 | #define I2C4_BASE_SE (IO_PHYS + 0x1008000) |
| 23 | #define I2C2_BASE_SE (IO_PHYS + 0x1009000) |
| 24 | #define PMIC_WRAP_BASE (IO_PHYS + 0xd000) |
| 25 | #define MCUCFG_BASE 0x0c530000 |
| 26 | #define CFG_SF_CTRL 0x0c510014 |
| 27 | #define CFG_SF_INI 0x0c510010 |
| 28 | #define EMI_MPU_BASE (IO_PHYS + 0x226000) |
| 29 | #define TRNG_base (IO_PHYS + 0x20f000) |
| 30 | #define MT_GIC_BASE 0x0c000000 |
| 31 | #define PLAT_MT_CCI_BASE 0x0c500000 |
| 32 | #define CCI_SIZE 0x00010000 |
| 33 | #define EINT_BASE 0x1000b000 |
| 34 | #define DVFSRC_BASE (IO_PHYS + 0x12000) |
| 35 | |
| 36 | #define SSPM_CFGREG_BASE (IO_PHYS + 0x440000) |
| 37 | #define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000) |
| 38 | |
| 39 | #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) |
| 40 | |
| 41 | #define APMIXEDSYS (IO_PHYS + 0xC000) |
| 42 | #define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200) |
| 43 | #define ARMPLL_L_CON0 (APMIXEDSYS + 0x210) |
| 44 | #define MAINPLL_CON0 (APMIXEDSYS + 0x220) |
| 45 | #define CCIPLL_CON0 (APMIXEDSYS + 0x290) |
| 46 | |
| 47 | #define TOP_CKMUXSEL (INFRACFG_AO_BASE + 0x0) |
| 48 | |
| 49 | #define armpll_mux1_sel_big_mask (0xf << 4) |
| 50 | #define armpll_mux1_sel_big_ARMSPLL (0x1 << 4) |
| 51 | #define armpll_mux1_sel_sml_mask (0xf << 8) |
| 52 | #define armpll_mux1_sel_sml_ARMSPLL (0x1 << 8) |
| 53 | |
| 54 | |
| 55 | /* Aggregate of all devices in the first GB */ |
| 56 | #define MTK_DEV_RNG0_BASE IO_PHYS |
| 57 | #define MTK_DEV_RNG0_SIZE 0x490000 |
| 58 | #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) |
| 59 | #define MTK_DEV_RNG1_SIZE 0x4000000 |
| 60 | #define MTK_DEV_RNG2_BASE 0x0c000000 |
| 61 | #define MTK_DEV_RNG2_SIZE 0x600000 |
| 62 | #define MT_MCUSYS_SIZE 0x90000 |
| 63 | #define RAM_CONSOLE_BASE 0x11d000 |
| 64 | #define RAM_CONSOLE_SIZE 0x1000 |
| 65 | |
| 66 | /******************************************************************************* |
| 67 | * MSDC |
| 68 | ******************************************************************************/ |
| 69 | #define MSDC0_BASE (IO_PHYS + 0x01230000) |
| 70 | |
| 71 | /******************************************************************************* |
| 72 | * MCUSYS related constants |
| 73 | ******************************************************************************/ |
| 74 | #define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604) |
| 75 | #define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0) |
| 76 | #define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4) |
| 77 | |
| 78 | /******************************************************************************* |
| 79 | * GIC related constants |
| 80 | ******************************************************************************/ |
| 81 | #define MT_POLARITY_LOW 0 |
| 82 | #define MT_POLARITY_HIGH 1 |
| 83 | #define MT_EDGE_SENSITIVE 1 |
| 84 | #define MT_LEVEL_SENSITIVE 0 |
| 85 | |
| 86 | /******************************************************************************* |
| 87 | * UART related constants |
| 88 | ******************************************************************************/ |
| 89 | #define UART0_BASE (IO_PHYS + 0x01002000) |
| 90 | |
| 91 | #define UART_BAUDRATE 115200 |
| 92 | #define UART_CLOCK 26000000 |
| 93 | |
| 94 | /******************************************************************************* |
| 95 | * System counter frequency related constants |
| 96 | ******************************************************************************/ |
| 97 | #define SYS_COUNTER_FREQ_IN_TICKS 13000000 |
| 98 | #define SYS_COUNTER_FREQ_IN_MHZ 13 |
| 99 | |
| 100 | /******************************************************************************* |
| 101 | * GIC-400 & interrupt handling related constants |
| 102 | ******************************************************************************/ |
| 103 | |
| 104 | /* Base MTK_platform compatible GIC memory map */ |
| 105 | #define BASE_GICD_BASE MT_GIC_BASE |
| 106 | #define BASE_GICC_BASE (MT_GIC_BASE + 0x400000) |
| 107 | #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x100000) |
| 108 | #define BASE_GICR_BASE (MT_GIC_BASE + 0x100000) |
| 109 | #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) |
| 110 | #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) |
| 111 | #define INT_POL_CTL0 (MCUCFG_BASE + 0xa80) |
| 112 | #define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00) |
| 113 | #define GIC_SYNC_DCM (MCUCFG_BASE + 0x758) |
| 114 | #define GIC_SYNC_DCM_MASK 0x3 |
| 115 | #define GIC_SYNC_DCM_ON 0x3 |
| 116 | #define GIC_SYNC_DCM_OFF 0x0 |
| 117 | #define GIC_PRIVATE_SIGNALS 32 |
| 118 | |
| 119 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 120 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 121 | |
| 122 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) ( \ |
| 123 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 124 | GIC_INTR_CFG_EDGE), \ |
| 125 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 126 | GIC_INTR_CFG_EDGE), \ |
| 127 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 128 | GIC_INTR_CFG_EDGE), \ |
| 129 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 130 | GIC_INTR_CFG_EDGE), \ |
| 131 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 132 | GIC_INTR_CFG_EDGE), \ |
| 133 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 134 | GIC_INTR_CFG_EDGE), \ |
| 135 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 136 | GIC_INTR_CFG_EDGE), \ |
| 137 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 138 | GIC_INTR_CFG_EDGE)) \ |
| 139 | |
| 140 | #define PLAT_ARM_G0_IRQ_PROPS(grp) |
| 141 | |
| 142 | /******************************************************************************* |
| 143 | * CCI-400 related constants |
| 144 | ******************************************************************************/ |
| 145 | #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 146 | #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 |
| 147 | |
| 148 | /******************************************************************************* |
| 149 | * WDT Registers |
| 150 | ******************************************************************************/ |
| 151 | #define MTK_WDT_BASE (IO_PHYS + 0x00007000) |
| 152 | #define MTK_WDT_SIZE 0x1000 |
| 153 | #define MTK_WDT_MODE (MTK_WDT_BASE + 0x0000) |
| 154 | #define MTK_WDT_LENGTH (MTK_WDT_BASE + 0x0004) |
| 155 | #define MTK_WDT_RESTART (MTK_WDT_BASE + 0x0008) |
| 156 | #define MTK_WDT_STATUS (MTK_WDT_BASE + 0x000C) |
| 157 | #define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x0010) |
| 158 | #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) |
| 159 | #define MTK_WDT_SWSYSRST (MTK_WDT_BASE + 0x0018) |
| 160 | #define MTK_WDT_NONRST_REG (MTK_WDT_BASE + 0x0020) |
| 161 | #define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE + 0x0024) |
| 162 | #define MTK_WDT_REQ_MODE (MTK_WDT_BASE + 0x0030) |
| 163 | #define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE + 0x0034) |
| 164 | #define MTK_WDT_EXT_REQ_CON (MTK_WDT_BASE + 0x0038) |
| 165 | #define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE + 0x0040) |
| 166 | #define MTK_WDT_LATCH_CTL (MTK_WDT_BASE + 0x0044) |
| 167 | #define MTK_WDT_DEBUG_CTL2 (MTK_WDT_BASE + 0x00A0) |
| 168 | #define MTK_WDT_COUNTER (MTK_WDT_BASE + 0x0514) |
| 169 | |
| 170 | /* WDT_STATUS */ |
| 171 | #define MTK_WDT_STATUS_SPM_THERMAL_RST (1 << 0) |
| 172 | #define MTK_WDT_STATUS_SPM_RST (1 << 1) |
| 173 | #define MTK_WDT_STATUS_EINT_RST (1 << 2) |
| 174 | #define MTK_WDT_STATUS_SYSRST_RST (1 << 3) /* from PMIC */ |
| 175 | #define MTK_WDT_STATUS_DVFSP_RST (1 << 4) |
| 176 | #define MTK_WDT_STATUS_PMCU_RST (1 << 16) |
| 177 | #define MTK_WDT_STATUS_MDDBG_RST (1 << 17) |
| 178 | #define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1 << 18) |
| 179 | #define MTK_WDT_STATUS_DEBUG_RST (1 << 19) |
| 180 | #define MTK_WDT_STATUS_SECURITY_RST (1 << 28) |
| 181 | #define MTK_WDT_STATUS_IRQ_ASSERT (1 << 29) |
| 182 | #define MTK_WDT_STATUS_SW_WDT_RST (1 << 30) |
| 183 | #define MTK_WDT_STATUS_HW_WDT_RST (1 << 31) |
| 184 | |
| 185 | /* RGU other related */ |
| 186 | #define MTK_WDT_MODE_DUAL_MODE 0x0040 |
| 187 | #define MTK_WDT_MODE_IRQ 0x0008 |
| 188 | #define MTK_WDT_MODE_KEY 0x22000000 |
| 189 | #define MTK_WDT_MODE_EXTEN 0x0004 |
| 190 | #define MTK_WDT_SWRST_KEY 0x1209 |
| 191 | #define MTK_WDT_RESTART_KEY 0x1971 |
| 192 | |
| 193 | /******************************************************************************* |
| 194 | * TRNG Registers |
| 195 | ******************************************************************************/ |
| 196 | #define TRNG_BASE_ADDR TRNG_base |
| 197 | #define TRNG_BASE_SIZE 0x1000 |
| 198 | #define TRNG_CTRL (TRNG_base + 0x0000) |
| 199 | #define TRNG_TIME (TRNG_base + 0x0004) |
| 200 | #define TRNG_DATA (TRNG_base + 0x0008) |
| 201 | #define TRNG_PDN_base 0x10001000 |
| 202 | #define TRNG_PDN_BASE_ADDR TRNG_PDN_BASE_ADDR |
| 203 | #define TRNG_PDN_BASE_SIZE 0x1000 |
| 204 | #define TRNG_PDN_SET (TRNG_PDN_base + 0x0088) |
| 205 | #define TRNG_PDN_CLR (TRNG_PDN_base + 0x008c) |
| 206 | #define TRNG_PDN_STATUS (TRNG_PDN_base + 0x0094) |
| 207 | #define TRNG_CTRL_RDY 0x80000000 |
| 208 | #define TRNG_CTRL_START 0x00000001 |
| 209 | #define TRNG_PDN_VALUE 0x200 |
| 210 | |
| 211 | /* FIQ platform related define */ |
| 212 | #define MT_IRQ_SEC_SGI_0 8 |
| 213 | #define MT_IRQ_SEC_SGI_1 9 |
| 214 | #define MT_IRQ_SEC_SGI_2 10 |
| 215 | #define MT_IRQ_SEC_SGI_3 11 |
| 216 | #define MT_IRQ_SEC_SGI_4 12 |
| 217 | #define MT_IRQ_SEC_SGI_5 13 |
| 218 | #define MT_IRQ_SEC_SGI_6 14 |
| 219 | #define MT_IRQ_SEC_SGI_7 15 |
| 220 | |
| 221 | #define FIQ_SMP_CALL_SGI 13 |
| 222 | #define WDT_IRQ_BIT_ID 174 |
| 223 | #define ATF_LOG_IRQ_ID 277 |
| 224 | |
| 225 | #define ATF_AMMS_IRQ_ID 338 |
| 226 | #define PCCIF1_IRQ0_BIT_ID 185 |
| 227 | #define PCCIF1_IRQ1_BIT_ID 186 |
| 228 | |
| 229 | #define DEBUG_XLAT_TABLE 0 |
| 230 | |
| 231 | /******************************************************************************* |
| 232 | * Platform binary types for linking |
| 233 | ******************************************************************************/ |
| 234 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 235 | #define PLATFORM_LINKER_ARCH aarch64 |
| 236 | |
| 237 | /******************************************************************************* |
| 238 | * Generic platform constants |
| 239 | ******************************************************************************/ |
| 240 | |
| 241 | /* Size of cacheable stacks */ |
| 242 | #if DEBUG_XLAT_TABLE |
| 243 | #define PLATFORM_STACK_SIZE 0x800 |
| 244 | #elif IMAGE_BL1 |
| 245 | #define PLATFORM_STACK_SIZE 0x440 |
| 246 | #elif IMAGE_BL2 |
| 247 | #define PLATFORM_STACK_SIZE 0x400 |
| 248 | #elif IMAGE_BL31 |
| 249 | #define PLATFORM_STACK_SIZE 0x800 |
| 250 | #elif IMAGE_BL32 |
| 251 | #define PLATFORM_STACK_SIZE 0x440 |
| 252 | #endif |
| 253 | |
| 254 | #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" |
| 255 | #define PLAT_MAX_PWR_LVL U(2) |
| 256 | #define PLAT_MAX_RET_STATE U(1) |
| 257 | #define PLAT_MAX_OFF_STATE U(2) |
| 258 | |
| 259 | #define PLATFORM_CACHE_LINE_SIZE 64 |
| 260 | #define PLATFORM_SYSTEM_COUNT 1 |
| 261 | #define PLATFORM_CLUSTER_COUNT 2 |
| 262 | #define PLATFORM_CLUSTER0_CORE_COUNT 4 |
| 263 | #define PLATFORM_CLUSTER1_CORE_COUNT 4 |
| 264 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ |
| 265 | PLATFORM_CLUSTER0_CORE_COUNT) |
| 266 | #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 |
| 267 | #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ |
| 268 | PLATFORM_CLUSTER_COUNT + \ |
| 269 | PLATFORM_CORE_COUNT) |
| 270 | |
| 271 | /******************************************************************************* |
| 272 | * Platform memory map related constants |
| 273 | ******************************************************************************/ |
| 274 | |
| 275 | #define TZRAM_BASE 0x54600000 |
| 276 | #define TZRAM_SIZE 0x00020000 |
| 277 | |
| 278 | /******************************************************************************* |
| 279 | * BL31 specific defines. |
| 280 | ******************************************************************************/ |
| 281 | /* |
| 282 | * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if |
| 283 | * present). BL31_BASE is calculated using the current BL31 debug size plus a |
| 284 | * little space for growth. |
| 285 | */ |
| 286 | #define BL31_BASE (TZRAM_BASE + 0x1000) |
| 287 | #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) |
| 288 | |
| 289 | /******************************************************************************* |
| 290 | * Platform specific page table and MMU setup constants |
| 291 | ******************************************************************************/ |
| 292 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 293 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 294 | #define MAX_XLAT_TABLES 4 |
| 295 | #define MAX_MMAP_REGIONS 16 |
| 296 | |
| 297 | /******************************************************************************* |
| 298 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 299 | * aligned on the biggest cache line size in the platform. This is known only |
| 300 | * to the platform as it might have a combination of integrated and external |
| 301 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 302 | * line at any cache level. They could belong to different cpus/clusters & |
| 303 | * get written while being protected by different locks causing corruption of |
| 304 | * a valid mailbox address. |
| 305 | ******************************************************************************/ |
| 306 | #define CACHE_WRITEBACK_SHIFT 6 |
| 307 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 308 | #endif /* PLATFORM_DEF_H */ |