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git01.mediatek.com / filogic / atf / 5896f3d0c020d198d1871ac440840e727a6fc522 / . / drivers / staging / renesas / rcar / pfc / D3 / pfc_init_d3.c
blob: dccc7c35fe9483757c2725dfd7c7357860f4a6a6 [file] [log] [blame]
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]1/*
Marek Vasutf5846d22019-06-17 18:27:07 +0200[diff] [blame]2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdint.h>
Ambroise Vincentffbf32a2019-03-28 09:01:18 +0000[diff] [blame]8#include <lib/mmio.h>
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]9#include "pfc_init_d3.h"
10#include "rcar_def.h"
Marek Vasutad37fb62019-06-17 18:19:09 +0200[diff] [blame]11#include "../pfc_regs.h"
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]12
Marek Vasutad37fb62019-06-17 18:19:09 +0200[diff] [blame]13/* PFC */
Marek Vasut5896f3d2019-06-17 18:31:12 +0200[diff] [blame^]14#define GPSR0_D15 ((uint32_t)1U << 15U)
15#define GPSR0_D14 ((uint32_t)1U << 14U)
16#define GPSR0_D13 ((uint32_t)1U << 13U)
17#define GPSR0_D12 ((uint32_t)1U << 12U)
18#define GPSR0_D11 ((uint32_t)1U << 11U)
19#define GPSR0_D10 ((uint32_t)1U << 10U)
20#define GPSR0_D9 ((uint32_t)1U << 9U)
21#define GPSR0_D8 ((uint32_t)1U << 8U)
22#define GPSR0_D7 ((uint32_t)1U << 7U)
23#define GPSR0_D6 ((uint32_t)1U << 6U)
24#define GPSR0_D5 ((uint32_t)1U << 5U)
25#define GPSR0_D4 ((uint32_t)1U << 4U)
26#define GPSR0_D3 ((uint32_t)1U << 3U)
27#define GPSR0_D2 ((uint32_t)1U << 2U)
28#define GPSR0_D1 ((uint32_t)1U << 1U)
29#define GPSR0_D0 ((uint32_t)1U << 0U)
30#define GPSR1_CLKOUT ((uint32_t)1U << 28U)
31#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
32#define GPSR1_WE1 ((uint32_t)1U << 26U)
33#define GPSR1_WE0 ((uint32_t)1U << 25U)
34#define GPSR1_RD_WR ((uint32_t)1U << 24U)
35#define GPSR1_RD ((uint32_t)1U << 23U)
36#define GPSR1_BS ((uint32_t)1U << 22U)
37#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
38#define GPSR1_CS0 ((uint32_t)1U << 20U)
39#define GPSR1_A19 ((uint32_t)1U << 19U)
40#define GPSR1_A18 ((uint32_t)1U << 18U)
41#define GPSR1_A17 ((uint32_t)1U << 17U)
42#define GPSR1_A16 ((uint32_t)1U << 16U)
43#define GPSR1_A15 ((uint32_t)1U << 15U)
44#define GPSR1_A14 ((uint32_t)1U << 14U)
45#define GPSR1_A13 ((uint32_t)1U << 13U)
46#define GPSR1_A12 ((uint32_t)1U << 12U)
47#define GPSR1_A11 ((uint32_t)1U << 11U)
48#define GPSR1_A10 ((uint32_t)1U << 10U)
49#define GPSR1_A9 ((uint32_t)1U << 9U)
50#define GPSR1_A8 ((uint32_t)1U << 8U)
51#define GPSR1_A7 ((uint32_t)1U << 7U)
52#define GPSR1_A6 ((uint32_t)1U << 6U)
53#define GPSR1_A5 ((uint32_t)1U << 5U)
54#define GPSR1_A4 ((uint32_t)1U << 4U)
55#define GPSR1_A3 ((uint32_t)1U << 3U)
56#define GPSR1_A2 ((uint32_t)1U << 2U)
57#define GPSR1_A1 ((uint32_t)1U << 1U)
58#define GPSR1_A0 ((uint32_t)1U << 0U)
59#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
60#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
61#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
62#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
63#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
64#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
65#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
66#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
67#define GPSR2_PWM0 ((uint32_t)1U << 6U)
68#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
69#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
70#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
71#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
72#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
73#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
74#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
75#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
76#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
77#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
78#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
79#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
80#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
81#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
82#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
83#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
84#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
85#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
86#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
87#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
88#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
89#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
90#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
91#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
92#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
93#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
94#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
95#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
96#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
97#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
98#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
99#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
100#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
101#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
102#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
103#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
104#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
105#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
106#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
107#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
108#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
109#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
110#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
111#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
112#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
113#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
114#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
115#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
116#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
117#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
118#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
119#define GPSR5_HTX0 ((uint32_t)1U << 14U)
120#define GPSR5_HRX0 ((uint32_t)1U << 13U)
121#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
122#define GPSR5_RX2_A ((uint32_t)1U << 11U)
123#define GPSR5_TX2_A ((uint32_t)1U << 10U)
124#define GPSR5_SCK2 ((uint32_t)1U << 9U)
125#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
126#define GPSR5_CTS1 ((uint32_t)1U << 7U)
127#define GPSR5_TX1_A ((uint32_t)1U << 6U)
128#define GPSR5_RX1_A ((uint32_t)1U << 5U)
129#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
130#define GPSR5_CTS0 ((uint32_t)1U << 3U)
131#define GPSR5_TX0 ((uint32_t)1U << 2U)
132#define GPSR5_RX0 ((uint32_t)1U << 1U)
133#define GPSR5_SCK0 ((uint32_t)1U << 0U)
134#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
135#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
136#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
137#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
138#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
139#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
140#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
141#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
142#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
143#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
144#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
145#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
146#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
147#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
148#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
149#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
150#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
151#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
152#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
153#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
154#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
155#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
156#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
157#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
158#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
159#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
160#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
161#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
162#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
163#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
164#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
165#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
166#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
167#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
168#define GPSR7_AVS2 ((uint32_t)1U << 1U)
169#define GPSR7_AVS1 ((uint32_t)1U << 0U)
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]170
Marek Vasut5896f3d2019-06-17 18:31:12 +0200[diff] [blame^]171#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
172#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
173#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
174#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
175#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
176#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
177#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
178#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]179
Marek Vasut5896f3d2019-06-17 18:31:12 +0200[diff] [blame^]180#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
181#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
182#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
183#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
184#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
185#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
186#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
187#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
188#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
189#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
190#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
191#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
192#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
193#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
194#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
195#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
196#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
197#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
198#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
199#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
200#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
201#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
202#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
203#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
204#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
205#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
206#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
207#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
208#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
209#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]210
Marek Vasut5896f3d2019-06-17 18:31:12 +0200[diff] [blame^]211#define DRVCTRL0_MASK (0xCCCCCCCCU)
212#define DRVCTRL1_MASK (0xCCCCCCC8U)
213#define DRVCTRL2_MASK (0x88888888U)
214#define DRVCTRL3_MASK (0x88888888U)
215#define DRVCTRL4_MASK (0x88888888U)
216#define DRVCTRL5_MASK (0x88888888U)
217#define DRVCTRL6_MASK (0x88888888U)
218#define DRVCTRL7_MASK (0x88888888U)
219#define DRVCTRL8_MASK (0x88888888U)
220#define DRVCTRL9_MASK (0x88888888U)
221#define DRVCTRL10_MASK (0x88888888U)
222#define DRVCTRL11_MASK (0x888888CCU)
223#define DRVCTRL12_MASK (0xCCCFFFCFU)
224#define DRVCTRL13_MASK (0xCC888888U)
225#define DRVCTRL14_MASK (0x88888888U)
226#define DRVCTRL15_MASK (0x88888888U)
227#define DRVCTRL16_MASK (0x88888888U)
228#define DRVCTRL17_MASK (0x88888888U)
229#define DRVCTRL18_MASK (0x88888888U)
230#define DRVCTRL19_MASK (0x88888888U)
231#define DRVCTRL20_MASK (0x88888888U)
232#define DRVCTRL21_MASK (0x88888888U)
233#define DRVCTRL22_MASK (0x88888888U)
234#define DRVCTRL23_MASK (0x88888888U)
235#define DRVCTRL24_MASK (0x8888888FU)
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]236
Marek Vasut5896f3d2019-06-17 18:31:12 +0200[diff] [blame^]237#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
238#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
239#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
240#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
241#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
242#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
243#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
244#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
245#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
246#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
247#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
248#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
249#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
250#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
251#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
252#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
253#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
254#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
255#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
256#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
257#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
258#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
259#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
260#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
261#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
262#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
263#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
264#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
265#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
266#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
267#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
268#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
269#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
270#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
271#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
272#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
273#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
274#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
275#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
276#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
277#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
278#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
279#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
280#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
281#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
282#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
283#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
284#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
285#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
286#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
287#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
288#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
289#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
290#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
291#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
292#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
293#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
294#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
295#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
296#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
297#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
298#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
299#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
300#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
301#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
302#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
303#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
304#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
305#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
306#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
307#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
308#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
309#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
310#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
311#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
312#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
313#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
314#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
315#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
316#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
317#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
318#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
319#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
320#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
321#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
322#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
323#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
324#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
325#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
326#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
327#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
328#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
329#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
330#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
331#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
332#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
333#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
334#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
335#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
336#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
337#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
338#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
339#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
340#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
341#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
342#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
343#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
344#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
345#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
346#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
347#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
348#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
349#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
350#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
351#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
352#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
353#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
354#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
355#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
356#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
357#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
358#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
359#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
360#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
361#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
362#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
363#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
364#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
365#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
366#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
367#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
368#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
369#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
370#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
371#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
372#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
373#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
374#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
375#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
376#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
377#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
378#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
379#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
380#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
381#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
382#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
383#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
384#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
385#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
386#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
387#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
388#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
389#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
390#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
391#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
392#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
393#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
394#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
395#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
396#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
397#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
398#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
399#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
400#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
401#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
402#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
403#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
404#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
405#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
406#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
407#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
408#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
409#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
410#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
411#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
412#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
413#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
414#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
415#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
416#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
417#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
418#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
419#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
420#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
421#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
422#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
423#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
424#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
425#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
426#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
427#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
428#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
429#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
430#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
431#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]432
Marek Vasut5896f3d2019-06-17 18:31:12 +0200[diff] [blame^]433#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
434#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
435#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
436#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
437#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
438#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
439#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
440#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
441#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
442#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
443#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
444#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
445#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
446#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
447#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
448#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
449#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
450#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
451#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
452#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
453#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
454#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
455#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
456#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
457#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
458#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
459#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
460#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
461#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
462#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
463#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
464#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
465#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
466#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
467#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
468#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
469#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
470#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
471#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
472#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
473#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
474#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
475#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
476#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
477#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
478#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
479#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
480#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
481#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
482#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
483#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
484#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
485#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
486#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
487#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
488#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
489#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
490#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
491#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
492#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
493#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
494#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
495#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
496#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
497#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
498#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
499#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
500#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
501#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
502#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
503#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
504#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
505#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
506#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
507#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
508#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
509#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
510#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
511#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
512#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
513#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
514#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
515#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
516#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
517#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
518#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
519#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
520#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
521#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
522#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
523#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
524#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
525#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
526#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
527#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
528#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
529#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
530#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
531#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
532#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
533#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
534#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
535#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
536#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
537#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
538#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
539#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
540#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
541#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
542#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
543#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
544#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
545#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
546#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
547#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
548#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
549#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
550#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
551#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
552#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
553#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
554#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
555#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
556#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
557#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
558#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
559#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
560#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
561#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
562#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
563#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
564#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
565#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
566#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
567#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
568#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
569#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
570#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
571#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
572#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]573
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]574/* Realtime module stop control */
Marek Vasut5896f3d2019-06-17 18:31:12 +0200[diff] [blame^]575#define CPG_BASE (0xE6150000U)
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]576#define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
577#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U)
578#define RMSTPCR0_RTDMAC (0x00200000U)
579
580/* RT-DMAC Registers */
581#define RTDMAC_CH (0U) /* choose 0 to 15 */
582
583#define RTDMAC_BASE (0xFFC10000U)
584#define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U)
585#define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U)
586#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x)))
587#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x)))
588#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x)))
589#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x)))
590#define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x)))
591#define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x)))
592#define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U)
593#define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U)
594#define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U)
595#define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U)
596
597#define RDMOR_DME (0x0001U) /* DMA Master Enable */
598#define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */
599#define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */
600#define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */
601#define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */
602#define RDMCHCR_DE (0x00000001U) /* DMA Enable */
603#define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */
604#define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */
605#define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */
606
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]607static void pfc_reg_write(uint32_t addr, uint32_t data)
608{
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]609 mmio_write_32(PFC_PMMR, ~data);
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]610 mmio_write_32((uintptr_t)addr, data);
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]611}
612
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]613void pfc_init_d3(void)
614{
615 /* initialize module select */
616 pfc_reg_write(PFC_MOD_SEL0, 0x00000000U);
617 pfc_reg_write(PFC_MOD_SEL1, 0x00000000U);
618
619 /* initialize peripheral function select */
620 pfc_reg_write(PFC_IPSR0, 0x00000001U);
621 pfc_reg_write(PFC_IPSR1, 0x00000000U);
622 pfc_reg_write(PFC_IPSR2, 0x00000000U);
623 pfc_reg_write(PFC_IPSR3, 0x00000000U);
624 pfc_reg_write(PFC_IPSR4, 0x00002000U);
625 pfc_reg_write(PFC_IPSR5, 0x00000000U);
626 pfc_reg_write(PFC_IPSR6, 0x00000000U);
627 pfc_reg_write(PFC_IPSR7, 0x00000000U);
628 pfc_reg_write(PFC_IPSR8, 0x11003301U);
629 pfc_reg_write(PFC_IPSR9, 0x11111111U);
630 pfc_reg_write(PFC_IPSR10, 0x00020000U);
631 pfc_reg_write(PFC_IPSR11, 0x40001110U);
632 pfc_reg_write(PFC_IPSR12, 0x00000000U);
633 pfc_reg_write(PFC_IPSR13, 0x00000000U);
634
635 /* initialize GPIO/perihperal function select */
636 pfc_reg_write(PFC_GPSR0, 0x0000001FU);
637 pfc_reg_write(PFC_GPSR1, 0x3FFFFFFFU);
638 pfc_reg_write(PFC_GPSR2, 0xFFFFFFFFU);
639 pfc_reg_write(PFC_GPSR3, 0x000003FFU);
640 pfc_reg_write(PFC_GPSR4, 0xFC7F0F7EU);
641 pfc_reg_write(PFC_GPSR5, 0x001BFFFBU);
642 pfc_reg_write(PFC_GPSR6, 0x00003FFFU);
643
644 /* initialize POC control register */
645 pfc_reg_write(PFC_POCCTRL0, 0xC00FFFFFU);
646 pfc_reg_write(PFC_POCCTRL1, 0XFFFFFFFEU);
647 pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
648
649 /* initialize LSI pin pull-up/down control */
650 pfc_reg_write(PFC_PUD0, 0x0047C1A2U);
651 pfc_reg_write(PFC_PUD1, 0x4E13ABFFU);
652 pfc_reg_write(PFC_PUD2, 0xFFFFFFFFU);
653 pfc_reg_write(PFC_PUD3, 0xFF0FFFFFU);
654 pfc_reg_write(PFC_PUD4, 0xE0000000U);
655 pfc_reg_write(PFC_PUD5, 0x60000000U);
Ambroise Vincentffbf32a2019-03-28 09:01:18 +0000[diff] [blame]656
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]657 /* initialize LSI pin pull-enable register */
658 pfc_reg_write(PFC_PUEN0, 0x00000000U);
659 pfc_reg_write(PFC_PUEN1, 0x00000000U);
660 pfc_reg_write(PFC_PUEN2, 0x00000000U);
661 pfc_reg_write(PFC_PUEN3, 0x000F008CU);
662 pfc_reg_write(PFC_PUEN4, 0x00000000U);
663 pfc_reg_write(PFC_PUEN5, 0x00000000U);
Ambroise Vincentffbf32a2019-03-28 09:01:18 +0000[diff] [blame]664
Marek Vasut6f4984c2018-06-14 06:26:45 +0200[diff] [blame]665 /* initialize positive/negative logic select */
666 mmio_write_32(GPIO_POSNEG0, 0x00000000U);
667 mmio_write_32(GPIO_POSNEG1, 0x00000000U);
668 mmio_write_32(GPIO_POSNEG2, 0x00000000U);
669 mmio_write_32(GPIO_POSNEG3, 0x00000000U);
670 mmio_write_32(GPIO_POSNEG4, 0x00000000U);
671 mmio_write_32(GPIO_POSNEG5, 0x00000000U);
672 mmio_write_32(GPIO_POSNEG6, 0x00000000U);
673
674 /* initialize general IO/interrupt switching */
675 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
676 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
677 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
678 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
679 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
680 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
681 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
682
683 /* initialize general output register */
684 mmio_write_32(GPIO_OUTDT0, 0x00000000U);
685 mmio_write_32(GPIO_OUTDT1, 0x00000000U);
686 mmio_write_32(GPIO_OUTDT2, 0x00000400U);
687 mmio_write_32(GPIO_OUTDT3, 0x00000000U);
688 mmio_write_32(GPIO_OUTDT4, 0x00000000U);
689 mmio_write_32(GPIO_OUTDT5, 0x00000006U);
690 mmio_write_32(GPIO_OUTDT6, 0x00003880U);
691
692 /* initialize general input/output switching */
693 mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
694 mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
695 mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
696 mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
697 mmio_write_32(GPIO_INOUTSEL4, 0x00802000U);
698 mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
699 mmio_write_32(GPIO_INOUTSEL6, 0x00000000U);
700}