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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
7#ifndef __PLAT_DEF_H__
8#define __PLAT_DEF_H__
9
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080010#include <addressmap.h>
Tony Xief6118cc2016-01-15 17:17:32 +080011
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080012#define RK3399_PRIMARY_CPU 0x0
Caesar Wang038f6aa2016-05-25 19:21:43 +080013
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080014/* Special value used to verify platform parameters from BL2 to BL3-1 */
15#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
Tony Xief6118cc2016-01-15 17:17:32 +080016
17/**************************************************************************
18 * UART related constants
19 **************************************************************************/
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080020#define RK3399_BAUDRATE 115200
21#define RK3399_UART_CLOCK 24000000
Tony Xief6118cc2016-01-15 17:17:32 +080022
23/******************************************************************************
24 * System counter frequency related constants
25 ******************************************************************************/
26#define SYS_COUNTER_FREQ_IN_TICKS 24000000
Tony Xief6118cc2016-01-15 17:17:32 +080027
28/* Base rockchip_platform compatible GIC memory map */
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080029#define BASE_GICD_BASE (GIC500_BASE)
30#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1))
Tony Xief6118cc2016-01-15 17:17:32 +080031
32/*****************************************************************************
33 * CCI-400 related constants
34 ******************************************************************************/
35#define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0
36#define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1
37
38/******************************************************************************
Tony Xief6118cc2016-01-15 17:17:32 +080039 * sgi, ppi
40 ******************************************************************************/
41#define ARM_IRQ_SEC_PHY_TIMER 29
42
43#define ARM_IRQ_SEC_SGI_0 8
44#define ARM_IRQ_SEC_SGI_1 9
45#define ARM_IRQ_SEC_SGI_2 10
46#define ARM_IRQ_SEC_SGI_3 11
47#define ARM_IRQ_SEC_SGI_4 12
48#define ARM_IRQ_SEC_SGI_5 13
49#define ARM_IRQ_SEC_SGI_6 14
50#define ARM_IRQ_SEC_SGI_7 15
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080051
Tony Xief6118cc2016-01-15 17:17:32 +080052/*
53 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
54 * terminology. On a GICv2 system or mode, the lists will be merged and treated
55 * as Group 0 interrupts.
56 */
Antonio Nino Diaz58230902018-09-24 17:16:20 +010057#define PLAT_RK_GICV3_G1S_IRQS \
58 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
59 INTR_GROUP1S, GIC_INTR_CFG_LEVEL)
60
61#define PLAT_RK_GICV3_G0_IRQS \
62 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
63 INTR_GROUP0, GIC_INTR_CFG_LEVEL)
Tony Xief6118cc2016-01-15 17:17:32 +080064
Tony Xief6118cc2016-01-15 17:17:32 +080065#endif /* __PLAT_DEF_H__ */