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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
7#ifndef __PLAT_DEF_H__
8#define __PLAT_DEF_H__
9
10/* Special value used to verify platform parameters from BL2 to BL3-1 */
11#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
12
13#define CCI400_BASE 0xffb90000
14#define CCI400_SIZE 0x10000
15
16#define GIC400_BASE 0xffb70000
17#define GIC400_SIZE 0x10000
18
19#define STIME_BASE 0xff830000
20#define STIME_SIZE 0x10000
21
22#define CRU_BASE 0xff760000
23#define CRU_SIZE 0x10000
24
25#define GRF_BASE 0xff770000
26#define GRF_SIZE 0x10000
27
28#define SGRF_BASE 0xff740000
29#define SGRF_SIZE 0x10000
30
31#define PMU_BASE 0xff730000
32#define PMU_GRF_BASE 0xff738000
33#define PMU_SIZE 0x10000
34
35#define RK_INTMEM_BASE 0xff8c0000
36#define RK_INTMEM_SIZE 0x10000
37
38#define UART_DBG_BASE 0xff690000
39#define UART_DBG_SIZE 0x10000
40
41#define CRU_BASE 0xff760000
42
43#define PMUSRAM_BASE 0xff720000
44#define PMUSRAM_SIZE 0x10000
45#define PMUSRAM_RSIZE 0x1000
46
47#define DDR_PCTL_BASE 0xff610000
48#define DDR_PCTL_SIZE 0x10000
49
50#define DDR_PHY_BASE 0xff620000
51#define DDR_PHY_SIZE 0x10000
52
53#define SERVICE_BUS_BASE 0xffac0000
54#define SERVICE_BUS_SISE 0x50000
55
56#define COLD_BOOT_BASE 0xffff0000
57/**************************************************************************
58 * UART related constants
59 **************************************************************************/
60#define RK3368_UART2_BASE UART_DBG_BASE
61#define RK3368_BAUDRATE 115200
62#define RK3368_UART_CLOCK 24000000
63
64/******************************************************************************
65 * System counter frequency related constants
66 ******************************************************************************/
67#define SYS_COUNTER_FREQ_IN_TICKS 24000000
Tony Xief6118cc2016-01-15 17:17:32 +080068
69/******************************************************************************
70 * GIC-400 & interrupt handling related constants
71 ******************************************************************************/
72
73/* Base rk_platform compatible GIC memory map */
74#define RK3368_GICD_BASE (GIC400_BASE + 0x1000)
75#define RK3368_GICC_BASE (GIC400_BASE + 0x2000)
76#define RK3368_GICR_BASE 0 /* no GICR in GIC-400 */
77
78/*****************************************************************************
79 * CCI-400 related constants
80 ******************************************************************************/
81#define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 3
82#define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 4
83
84/******************************************************************************
Tony Xief6118cc2016-01-15 17:17:32 +080085 * sgi, ppi
86 ******************************************************************************/
87#define RK_IRQ_SEC_PHY_TIMER 29
88
89#define RK_IRQ_SEC_SGI_0 8
90#define RK_IRQ_SEC_SGI_1 9
91#define RK_IRQ_SEC_SGI_2 10
92#define RK_IRQ_SEC_SGI_3 11
93#define RK_IRQ_SEC_SGI_4 12
94#define RK_IRQ_SEC_SGI_5 13
95#define RK_IRQ_SEC_SGI_6 14
96#define RK_IRQ_SEC_SGI_7 15
97
98/*
99 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
100 * terminology. On a GICv2 system or mode, the lists will be merged and treated
101 * as Group 0 interrupts.
102 */
Antonio Nino Diaz58230902018-09-24 17:16:20 +0100103#define PLAT_RK_GICV2_G1S_IRQS \
104 INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
105 GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL)
Tony Xief6118cc2016-01-15 17:17:32 +0800106
107#endif /* __PLAT_DEF_H__ */