blob: 0bc5925b1465ddccb3f13899f91c525aaa3c2071 [file] [log] [blame]
Michal Simek91794362022-08-31 16:45:14 +02001# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -08003# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Michal Simek91794362022-08-31 16:45:14 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6
7PLAT_PATH := plat/xilinx/versal_net
8
Akshay Belsarecbb0c232022-10-11 15:12:02 +05309# A78 Erratum for SoC
10ERRATA_A78_AE_1941500 := 1
11ERRATA_A78_AE_1951502 := 1
12ERRATA_A78_AE_2376748 := 1
13ERRATA_A78_AE_2395408 := 1
14
Michal Simek91794362022-08-31 16:45:14 +020015override PROGRAMMABLE_RESET_ADDRESS := 1
16PSCI_EXTENDED_STATE_ID := 1
17SEPARATE_CODE_AND_RODATA := 1
18override RESET_TO_BL31 := 1
19PL011_GENERIC_UART := 1
20GIC_ENABLE_V4_EXTN := 0
21GICV3_SUPPORT_GIC600 := 1
Jay Buddhabhattic6daff02022-09-05 02:56:32 -070022TFA_NO_PM := 0
Michal Simek91794362022-08-31 16:45:14 +020023
24override CTX_INCLUDE_AARCH32_REGS := 0
25
Jay Buddhabhattic6daff02022-09-05 02:56:32 -070026ifdef TFA_NO_PM
27 $(eval $(call add_define,TFA_NO_PM))
28endif
29
Michal Simek91794362022-08-31 16:45:14 +020030ifdef VERSAL_NET_ATF_MEM_BASE
31 $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE))
32
33 ifndef VERSAL_NET_ATF_MEM_SIZE
34 $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE")
35 endif
36 $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE))
37
38 ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE
39 $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE))
40 endif
41endif
42
43ifdef VERSAL_NET_BL32_MEM_BASE
44 $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE))
45
46 ifndef VERSAL_NET_BL32_MEM_SIZE
47 $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE")
48 endif
49 $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE))
50endif
51
52USE_COHERENT_MEM := 0
53HW_ASSISTED_COHERENCY := 1
54
55VERSAL_NET_CONSOLE ?= pl011
Akshay Belsare50a29682023-01-18 15:54:12 +053056ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc))
Akshay Belsare0babc5f2023-01-13 14:40:37 +053057else
58 $(error Please define VERSAL_NET_CONSOLE)
59endif
60
Michal Simek91794362022-08-31 16:45:14 +020061$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE}))
62
63PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
64 -Iplat/xilinx/common/include/ \
Michal Simekaa5443e2022-09-19 14:04:55 +020065 -Iplat/xilinx/common/ipi_mailbox_service/ \
Michal Simekdc708ac2022-09-19 13:52:54 +020066 -I${PLAT_PATH}/include/ \
67 -Iplat/xilinx/versal/pm_service/
Michal Simek91794362022-08-31 16:45:14 +020068
69# Include GICv3 driver files
70include drivers/arm/gic/v3/gicv3.mk
71include lib/xlat_tables_v2/xlat_tables.mk
72include lib/libfdt/libfdt.mk
73
74PLAT_BL_COMMON_SOURCES := \
Akshay Belsare50a29682023-01-18 15:54:12 +053075 drivers/arm/dcc/dcc_console.c \
Michal Simek91794362022-08-31 16:45:14 +020076 drivers/delay_timer/delay_timer.c \
77 drivers/delay_timer/generic_delay_timer.c \
78 ${GICV3_SOURCES} \
79 drivers/arm/pl011/aarch64/pl011_console.S \
80 plat/arm/common/arm_common.c \
81 plat/common/plat_gicv3.c \
82 ${PLAT_PATH}/aarch64/versal_net_helpers.S \
83 ${PLAT_PATH}/aarch64/versal_net_common.c
84
85BL31_SOURCES += drivers/arm/cci/cci.c \
86 lib/cpus/aarch64/cortex_a78_ae.S \
87 lib/cpus/aarch64/cortex_a78.S \
Jay Buddhabhattic6daff02022-09-05 02:56:32 -070088 plat/common/plat_psci_common.c
89ifeq ($(TFA_NO_PM), 0)
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -080090BL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \
Jay Buddhabhattic6daff02022-09-05 02:56:32 -070091 plat/xilinx/common/pm_service/pm_ipi.c \
92 ${PLAT_PATH}/plat_psci_pm.c \
Jay Buddhabhatti26e138a2022-12-21 23:03:35 -080093 plat/xilinx/common/pm_service/pm_svc_main.c \
Jay Buddhabhattic6daff02022-09-05 02:56:32 -070094 ${PLAT_PATH}/pm_service/pm_client.c \
95 ${PLAT_PATH}/versal_net_ipi.c
96else
97BL31_SOURCES += ${PLAT_PATH}/plat_psci.c
98endif
99BL31_SOURCES += plat/xilinx/common/plat_startup.c \
Michal Simekaa5443e2022-09-19 14:04:55 +0200100 plat/xilinx/common/ipi.c \
101 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
Michal Simek91794362022-08-31 16:45:14 +0200102 ${PLAT_PATH}/bl31_versal_net_setup.c \
103 ${PLAT_PATH}/plat_topology.c \
104 common/fdt_fixup.c \
105 ${LIBFDT_SRCS} \
106 ${PLAT_PATH}/sip_svc_setup.c \
107 ${PLAT_PATH}/versal_net_gicv3.c \
108 ${XLAT_TABLES_LIB_SRCS}