rutigl@gmail.com | defbeed | 2023-03-19 09:19:05 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Copyright (c) 2017-2023 Nuvoton Technology Corp. |
| 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | */ |
| 8 | |
| 9 | #ifndef PLAT_NPCM845X_H |
| 10 | #define PLAT_NPCM845X_H |
| 11 | |
| 12 | #include <drivers/arm/gicv2.h> |
| 13 | #include <lib/psci/psci.h> |
| 14 | |
| 15 | unsigned int plat_calc_core_pos(uint64_t mpidr); |
| 16 | void npcm845x_mailbox_init(uintptr_t base_addr); |
| 17 | void plat_gic_driver_init(void); |
| 18 | void plat_gic_init(void); |
| 19 | void plat_gic_cpuif_enable(void); |
| 20 | void plat_gic_cpuif_disable(void); |
| 21 | void plat_gic_pcpu_init(void); |
| 22 | |
| 23 | void __dead2 npcm845x_system_off(void); |
| 24 | void __dead2 npcm845x_system_reset(void); |
| 25 | void npcm845x_pwr_domain_on_finish(const psci_power_state_t *target_state); |
| 26 | bool npcm845x_is_wakeup_src_irqsteer(void); |
| 27 | void __dead2 npcm845x_pwr_down_wfi(const psci_power_state_t *target_state); |
| 28 | void npcm845x_cpu_standby(plat_local_state_t cpu_state); |
| 29 | int npcm845x_validate_ns_entrypoint(uintptr_t entrypoint); |
| 30 | int npcm845x_pwr_domain_on(u_register_t mpidr); |
| 31 | int npcm845x_validate_power_state(unsigned int power_state, |
| 32 | psci_power_state_t *req_state); |
| 33 | |
| 34 | #if !ARM_BL31_IN_DRAM |
| 35 | void npcm845x_get_sys_suspend_power_state(psci_power_state_t *req_state); |
| 36 | #endif |
| 37 | |
| 38 | void __dead2 npcm845x_pwr_domain_pwr_down_wfi( |
| 39 | const psci_power_state_t *target_state); |
| 40 | void npcm845x_pwr_domain_suspend_finish(const psci_power_state_t *target_state); |
| 41 | void npcm845x_pwr_domain_suspend(const psci_power_state_t *target_state); |
| 42 | void npcm845x_pwr_domain_off(const psci_power_state_t *target_state); |
| 43 | void __init npcm845x_bl31_plat_arch_setup(void); |
| 44 | |
| 45 | #endif /* PLAT_NPCM845X_H */ |