blob: ebc5c2c3d41a5fb924273e9e2966eccb530639d9 [file] [log] [blame]
Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
Masahiro Yamadade634f82020-01-17 13:45:14 +09002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta7c88f3f2014-02-18 18:09:12 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7c88f3f2014-02-18 18:09:12 +00005 */
6
Masahiro Yamadade634f82020-01-17 13:45:14 +09007#include <platform_def.h>
8
Achin Gupta7c88f3f2014-02-18 18:09:12 +00009#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000010#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl32/tsp/tsp.h>
12#include <lib/xlat_tables/xlat_tables_defs.h>
13
Dan Handleye2c27f52014-08-01 17:58:27 +010014#include "../tsp_private.h"
Achin Gupta7c88f3f2014-02-18 18:09:12 +000015
16
17 .globl tsp_entrypoint
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010018 .globl tsp_vector_table
Achin Gupta7c88f3f2014-02-18 18:09:12 +000019
Soby Mathew9f71f702014-05-09 20:49:17 +010020
21
Achin Gupta7c88f3f2014-02-18 18:09:12 +000022 /* ---------------------------------------------
23 * Populate the params in x0-x7 from the pointer
24 * to the smc args structure in x0.
25 * ---------------------------------------------
26 */
27 .macro restore_args_call_smc
28 ldp x6, x7, [x0, #TSP_ARG6]
29 ldp x4, x5, [x0, #TSP_ARG4]
30 ldp x2, x3, [x0, #TSP_ARG2]
31 ldp x0, x1, [x0, #TSP_ARG0]
32 smc #0
33 .endm
34
Achin Gupta76717892014-05-09 11:42:56 +010035 .macro save_eret_context reg1 reg2
36 mrs \reg1, elr_el1
37 mrs \reg2, spsr_el1
38 stp \reg1, \reg2, [sp, #-0x10]!
39 stp x30, x18, [sp, #-0x10]!
40 .endm
41
42 .macro restore_eret_context reg1 reg2
43 ldp x30, x18, [sp], #0x10
44 ldp \reg1, \reg2, [sp], #0x10
45 msr elr_el1, \reg1
46 msr spsr_el1, \reg2
47 .endm
48
Julius Wernerb4c75e92017-08-01 15:16:36 -070049func tsp_entrypoint _align=3
Achin Gupta7c88f3f2014-02-18 18:09:12 +000050
Masahiro Yamadade634f82020-01-17 13:45:14 +090051#if ENABLE_PIE
52 /*
53 * ------------------------------------------------------------
54 * If PIE is enabled fixup the Global descriptor Table only
55 * once during primary core cold boot path.
56 *
57 * Compile time base address, required for fixup, is calculated
58 * using "pie_fixup" label present within first page.
59 * ------------------------------------------------------------
60 */
61 pie_fixup:
62 ldr x0, =pie_fixup
63 and x0, x0, #~(PAGE_SIZE - 1)
64 mov_imm x1, (BL32_LIMIT - BL32_BASE)
65 add x1, x1, x0
66 bl fixup_gdt_reloc
67#endif /* ENABLE_PIE */
68
Achin Gupta7c88f3f2014-02-18 18:09:12 +000069 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +000070 * Set the exception vector to something sane.
71 * ---------------------------------------------
72 */
Achin Guptaa4f50c22014-05-09 12:17:56 +010073 adr x0, tsp_exceptions
Achin Gupta7c88f3f2014-02-18 18:09:12 +000074 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +010075 isb
Achin Gupta7c88f3f2014-02-18 18:09:12 +000076
77 /* ---------------------------------------------
Achin Guptaed1744e2014-08-04 23:13:10 +010078 * Enable the SError interrupt now that the
79 * exception vectors have been setup.
80 * ---------------------------------------------
81 */
82 msr daifclr, #DAIF_ABT_BIT
83
84 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +010085 * Enable the instruction cache, stack pointer
John Tsichritzisd5a59602019-03-04 16:42:54 +000086 * and data access alignment checks and disable
87 * speculative loads.
Achin Gupta7c88f3f2014-02-18 18:09:12 +000088 * ---------------------------------------------
89 */
Achin Gupta9f098352014-07-18 18:38:28 +010090 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000091 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +010092 orr x0, x0, x1
John Tsichritzisd5a59602019-03-04 16:42:54 +000093 bic x0, x0, #SCTLR_DSSBS_BIT
Achin Gupta7c88f3f2014-02-18 18:09:12 +000094 msr sctlr_el1, x0
95 isb
96
97 /* ---------------------------------------------
Achin Guptae9c4a642015-09-11 16:03:13 +010098 * Invalidate the RW memory used by the BL32
99 * image. This includes the data and NOBITS
100 * sections. This is done to safeguard against
101 * possible corruption of this memory by dirty
102 * cache lines in a system cache as a result of
103 * use by an earlier boot loader stage.
104 * ---------------------------------------------
105 */
106 adr x0, __RW_START__
107 adr x1, __RW_END__
108 sub x1, x1, x0
109 bl inv_dcache_range
110
111 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000112 * Zero out NOBITS sections. There are 2 of them:
113 * - the .bss section;
114 * - the coherent memory section.
115 * ---------------------------------------------
116 */
117 ldr x0, =__BSS_START__
118 ldr x1, =__BSS_SIZE__
Douglas Raillard21362a92016-12-02 13:51:54 +0000119 bl zeromem
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000120
Soby Mathew2ae20432015-01-08 18:02:44 +0000121#if USE_COHERENT_MEM
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000122 ldr x0, =__COHERENT_RAM_START__
123 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
Douglas Raillard21362a92016-12-02 13:51:54 +0000124 bl zeromem
Soby Mathew2ae20432015-01-08 18:02:44 +0000125#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000126
127 /* --------------------------------------------
Achin Guptaf4a97092014-06-25 19:26:22 +0100128 * Allocate a stack whose memory will be marked
129 * as Normal-IS-WBWA when the MMU is enabled.
130 * There is no risk of reading stale stack
131 * memory after enabling the MMU as only the
132 * primary cpu is running at the moment.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000133 * --------------------------------------------
134 */
Soby Mathewda43b662015-07-08 21:45:46 +0100135 bl plat_set_my_stack
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000136
137 /* ---------------------------------------------
Douglas Raillard306593d2017-02-24 18:14:15 +0000138 * Initialize the stack protector canary before
139 * any C code is called.
140 * ---------------------------------------------
141 */
142#if STACK_PROTECTOR_ENABLED
143 bl update_stack_protector_canary
144#endif
145
146 /* ---------------------------------------------
Antonio Nino Diaze61ece02019-02-26 11:41:03 +0000147 * Perform TSP setup
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000148 * ---------------------------------------------
149 */
Antonio Nino Diaze61ece02019-02-26 11:41:03 +0000150 bl tsp_setup
151
Antonio Nino Diaze61ece02019-02-26 11:41:03 +0000152#if ENABLE_PAUTH
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100153 /* ---------------------------------------------
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100154 * Program APIAKey_EL1
155 * and enable pointer authentication
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100156 * ---------------------------------------------
157 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100158 bl pauth_init_enable_el1
Antonio Nino Diaze61ece02019-02-26 11:41:03 +0000159#endif /* ENABLE_PAUTH */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000160
161 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000162 * Jump to main function.
163 * ---------------------------------------------
164 */
165 bl tsp_main
166
167 /* ---------------------------------------------
168 * Tell TSPD that we are done initialising
169 * ---------------------------------------------
170 */
171 mov x1, x0
172 mov x0, #TSP_ENTRY_DONE
173 smc #0
174
175tsp_entrypoint_panic:
176 b tsp_entrypoint_panic
Kévin Petita877c252015-03-24 14:03:57 +0000177endfunc tsp_entrypoint
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000178
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100179
180 /* -------------------------------------------
181 * Table of entrypoint vectors provided to the
182 * TSPD for the various entrypoints
183 * -------------------------------------------
184 */
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100185vector_base tsp_vector_table
David Cunado28f69ab2017-04-05 11:34:03 +0100186 b tsp_yield_smc_entry
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100187 b tsp_fast_smc_entry
188 b tsp_cpu_on_entry
189 b tsp_cpu_off_entry
190 b tsp_cpu_resume_entry
191 b tsp_cpu_suspend_entry
Soby Mathewbec98512015-09-03 18:29:38 +0100192 b tsp_sel1_intr_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100193 b tsp_system_off_entry
194 b tsp_system_reset_entry
David Cunado28f69ab2017-04-05 11:34:03 +0100195 b tsp_abort_yield_smc_entry
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100196
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000197 /*---------------------------------------------
198 * This entrypoint is used by the TSPD when this
199 * cpu is to be turned off through a CPU_OFF
200 * psci call to ask the TSP to perform any
201 * bookeeping necessary. In the current
202 * implementation, the TSPD expects the TSP to
203 * re-initialise its state so nothing is done
204 * here except for acknowledging the request.
205 * ---------------------------------------------
206 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000207func tsp_cpu_off_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000208 bl tsp_cpu_off_main
209 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000210endfunc tsp_cpu_off_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000211
212 /*---------------------------------------------
Juan Castillo4dc4a472014-08-12 11:17:06 +0100213 * This entrypoint is used by the TSPD when the
214 * system is about to be switched off (through
215 * a SYSTEM_OFF psci call) to ask the TSP to
216 * perform any necessary bookkeeping.
217 * ---------------------------------------------
218 */
219func tsp_system_off_entry
220 bl tsp_system_off_main
221 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000222endfunc tsp_system_off_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100223
224 /*---------------------------------------------
225 * This entrypoint is used by the TSPD when the
226 * system is about to be reset (through a
227 * SYSTEM_RESET psci call) to ask the TSP to
228 * perform any necessary bookkeeping.
229 * ---------------------------------------------
230 */
231func tsp_system_reset_entry
232 bl tsp_system_reset_main
233 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000234endfunc tsp_system_reset_entry
Juan Castillo4dc4a472014-08-12 11:17:06 +0100235
236 /*---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000237 * This entrypoint is used by the TSPD when this
238 * cpu is turned on using a CPU_ON psci call to
239 * ask the TSP to initialise itself i.e. setup
240 * the mmu, stacks etc. Minimal architectural
241 * state will be initialised by the TSPD when
242 * this function is entered i.e. Caches and MMU
243 * will be turned off, the execution state
244 * will be aarch64 and exceptions masked.
245 * ---------------------------------------------
246 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000247func tsp_cpu_on_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000248 /* ---------------------------------------------
249 * Set the exception vector to something sane.
250 * ---------------------------------------------
251 */
Achin Guptaa4f50c22014-05-09 12:17:56 +0100252 adr x0, tsp_exceptions
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000253 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +0100254 isb
255
256 /* Enable the SError interrupt */
257 msr daifclr, #DAIF_ABT_BIT
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000258
259 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +0100260 * Enable the instruction cache, stack pointer
261 * and data access alignment checks
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000262 * ---------------------------------------------
263 */
Achin Gupta9f098352014-07-18 18:38:28 +0100264 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000265 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +0100266 orr x0, x0, x1
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000267 msr sctlr_el1, x0
268 isb
269
270 /* --------------------------------------------
Achin Guptae1aa5162014-06-26 09:58:52 +0100271 * Give ourselves a stack whose memory will be
272 * marked as Normal-IS-WBWA when the MMU is
273 * enabled.
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000274 * --------------------------------------------
275 */
Soby Mathewda43b662015-07-08 21:45:46 +0100276 bl plat_set_my_stack
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000277
Achin Guptae1aa5162014-06-26 09:58:52 +0100278 /* --------------------------------------------
Jeenu Viswambharan0859d2c2018-04-27 16:28:12 +0100279 * Enable MMU and D-caches together.
Achin Guptae1aa5162014-06-26 09:58:52 +0100280 * --------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000281 */
Jeenu Viswambharan0859d2c2018-04-27 16:28:12 +0100282 mov x0, #0
Dan Handleyb226a4d2014-05-16 14:08:45 +0100283 bl bl32_plat_enable_mmu
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000284
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100285#if ENABLE_PAUTH
286 /* ---------------------------------------------
287 * Program APIAKey_EL1
288 * and enable pointer authentication
289 * ---------------------------------------------
290 */
291 bl pauth_init_enable_el1
292#endif /* ENABLE_PAUTH */
293
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000294 /* ---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000295 * Enter C runtime to perform any remaining
296 * book keeping
297 * ---------------------------------------------
298 */
299 bl tsp_cpu_on_main
300 restore_args_call_smc
301
302 /* Should never reach here */
303tsp_cpu_on_entry_panic:
304 b tsp_cpu_on_entry_panic
Kévin Petita877c252015-03-24 14:03:57 +0000305endfunc tsp_cpu_on_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000306
307 /*---------------------------------------------
308 * This entrypoint is used by the TSPD when this
309 * cpu is to be suspended through a CPU_SUSPEND
310 * psci call to ask the TSP to perform any
311 * bookeeping necessary. In the current
312 * implementation, the TSPD saves and restores
313 * the EL1 state.
314 * ---------------------------------------------
315 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000316func tsp_cpu_suspend_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000317 bl tsp_cpu_suspend_main
318 restore_args_call_smc
Kévin Petita877c252015-03-24 14:03:57 +0000319endfunc tsp_cpu_suspend_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000320
Soby Mathewbec98512015-09-03 18:29:38 +0100321 /*-------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100322 * This entrypoint is used by the TSPD to pass
Soby Mathew78664242015-11-13 02:08:43 +0000323 * control for `synchronously` handling a S-EL1
324 * Interrupt which was triggered while executing
325 * in normal world. 'x0' contains a magic number
326 * which indicates this. TSPD expects control to
327 * be handed back at the end of interrupt
328 * processing. This is done through an SMC.
329 * The handover agreement is:
Achin Gupta76717892014-05-09 11:42:56 +0100330 *
331 * 1. PSTATE.DAIF are set upon entry. 'x1' has
332 * the ELR_EL3 from the non-secure state.
333 * 2. TSP has to preserve the callee saved
334 * general purpose registers, SP_EL1/EL0 and
335 * LR.
336 * 3. TSP has to preserve the system and vfp
337 * registers (if applicable).
338 * 4. TSP can use 'x0-x18' to enable its C
339 * runtime.
340 * 5. TSP returns to TSPD using an SMC with
Soby Mathewbec98512015-09-03 18:29:38 +0100341 * 'x0' = TSP_HANDLED_S_EL1_INTR
342 * ------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100343 */
Soby Mathewbec98512015-09-03 18:29:38 +0100344func tsp_sel1_intr_entry
Achin Gupta76717892014-05-09 11:42:56 +0100345#if DEBUG
Soby Mathew78664242015-11-13 02:08:43 +0000346 mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN
Achin Gupta76717892014-05-09 11:42:56 +0100347 cmp x0, x2
Soby Mathewbec98512015-09-03 18:29:38 +0100348 b.ne tsp_sel1_int_entry_panic
Achin Gupta76717892014-05-09 11:42:56 +0100349#endif
Soby Mathewbec98512015-09-03 18:29:38 +0100350 /*-------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100351 * Save any previous context needed to perform
352 * an exception return from S-EL1 e.g. context
Soby Mathewbec98512015-09-03 18:29:38 +0100353 * from a previous Non secure Interrupt.
354 * Update statistics and handle the S-EL1
355 * interrupt before returning to the TSPD.
Achin Gupta76717892014-05-09 11:42:56 +0100356 * IRQ/FIQs are not enabled since that will
357 * complicate the implementation. Execution
358 * will be transferred back to the normal world
Soby Mathew78664242015-11-13 02:08:43 +0000359 * in any case. The handler can return 0
360 * if the interrupt was handled or TSP_PREEMPTED
361 * if the expected interrupt was preempted
362 * by an interrupt that should be handled in EL3
363 * e.g. Group 0 interrupt in GICv3. In both
364 * the cases switch to EL3 using SMC with id
365 * TSP_HANDLED_S_EL1_INTR. Any other return value
366 * from the handler will result in panic.
Soby Mathewbec98512015-09-03 18:29:38 +0100367 * ------------------------------------------------
Achin Gupta76717892014-05-09 11:42:56 +0100368 */
369 save_eret_context x2 x3
Soby Mathewbec98512015-09-03 18:29:38 +0100370 bl tsp_update_sync_sel1_intr_stats
371 bl tsp_common_int_handler
Soby Mathew78664242015-11-13 02:08:43 +0000372 /* Check if the S-EL1 interrupt has been handled */
373 cbnz x0, tsp_sel1_intr_check_preemption
374 b tsp_sel1_intr_return
375tsp_sel1_intr_check_preemption:
376 /* Check if the S-EL1 interrupt has been preempted */
377 mov_imm x1, TSP_PREEMPTED
378 cmp x0, x1
379 b.ne tsp_sel1_int_entry_panic
380tsp_sel1_intr_return:
381 mov_imm x0, TSP_HANDLED_S_EL1_INTR
Achin Gupta76717892014-05-09 11:42:56 +0100382 restore_eret_context x2 x3
Achin Gupta76717892014-05-09 11:42:56 +0100383 smc #0
384
Soby Mathew78664242015-11-13 02:08:43 +0000385 /* Should never reach here */
Soby Mathewbec98512015-09-03 18:29:38 +0100386tsp_sel1_int_entry_panic:
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000387 no_ret plat_panic_handler
Soby Mathewbec98512015-09-03 18:29:38 +0100388endfunc tsp_sel1_intr_entry
Achin Gupta76717892014-05-09 11:42:56 +0100389
390 /*---------------------------------------------
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000391 * This entrypoint is used by the TSPD when this
392 * cpu resumes execution after an earlier
393 * CPU_SUSPEND psci call to ask the TSP to
394 * restore its saved context. In the current
395 * implementation, the TSPD saves and restores
396 * EL1 state so nothing is done here apart from
397 * acknowledging the request.
398 * ---------------------------------------------
399 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000400func tsp_cpu_resume_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000401 bl tsp_cpu_resume_main
402 restore_args_call_smc
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000403
404 /* Should never reach here */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000405 no_ret plat_panic_handler
Kévin Petita877c252015-03-24 14:03:57 +0000406endfunc tsp_cpu_resume_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000407
408 /*---------------------------------------------
409 * This entrypoint is used by the TSPD to ask
410 * the TSP to service a fast smc request.
411 * ---------------------------------------------
412 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000413func tsp_fast_smc_entry
Soby Mathew9f71f702014-05-09 20:49:17 +0100414 bl tsp_smc_handler
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000415 restore_args_call_smc
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000416
417 /* Should never reach here */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000418 no_ret plat_panic_handler
Kévin Petita877c252015-03-24 14:03:57 +0000419endfunc tsp_fast_smc_entry
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000420
Soby Mathew9f71f702014-05-09 20:49:17 +0100421 /*---------------------------------------------
422 * This entrypoint is used by the TSPD to ask
David Cunado28f69ab2017-04-05 11:34:03 +0100423 * the TSP to service a Yielding SMC request.
Soby Mathew9f71f702014-05-09 20:49:17 +0100424 * We will enable preemption during execution
425 * of tsp_smc_handler.
426 * ---------------------------------------------
427 */
David Cunado28f69ab2017-04-05 11:34:03 +0100428func tsp_yield_smc_entry
Soby Mathew9f71f702014-05-09 20:49:17 +0100429 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
430 bl tsp_smc_handler
431 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
432 restore_args_call_smc
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000433
434 /* Should never reach here */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000435 no_ret plat_panic_handler
David Cunado28f69ab2017-04-05 11:34:03 +0100436endfunc tsp_yield_smc_entry
Douglas Raillardf2129652016-11-24 15:43:19 +0000437
438 /*---------------------------------------------------------------------
David Cunado28f69ab2017-04-05 11:34:03 +0100439 * This entrypoint is used by the TSPD to abort a pre-empted Yielding
Douglas Raillardf2129652016-11-24 15:43:19 +0000440 * SMC. It could be on behalf of non-secure world or because a CPU
441 * suspend/CPU off request needs to abort the preempted SMC.
442 * --------------------------------------------------------------------
443 */
David Cunado28f69ab2017-04-05 11:34:03 +0100444func tsp_abort_yield_smc_entry
Douglas Raillardf2129652016-11-24 15:43:19 +0000445
446 /*
447 * Exceptions masking is already done by the TSPD when entering this
448 * hook so there is no need to do it here.
449 */
450
451 /* Reset the stack used by the pre-empted SMC */
452 bl plat_set_my_stack
453
454 /*
455 * Allow some cleanup such as releasing locks.
456 */
457 bl tsp_abort_smc_handler
458
459 restore_args_call_smc
460
461 /* Should never reach here */
462 bl plat_panic_handler
David Cunado28f69ab2017-04-05 11:34:03 +0100463endfunc tsp_abort_yield_smc_entry