Caesar Wang | c1bf646 | 2016-06-21 14:44:01 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Caesar Wang | c1bf646 | 2016-06-21 14:44:01 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
Ziyuan Xu | 4060cfd | 2017-02-10 11:54:52 +0800 | [diff] [blame] | 7 | #include <cdn_dp.h> |
Caesar Wang | c1bf646 | 2016-06-21 14:44:01 +0800 | [diff] [blame] | 8 | #include <debug.h> |
| 9 | #include <mmio.h> |
| 10 | #include <plat_sip_calls.h> |
| 11 | #include <rockchip_sip_svc.h> |
| 12 | #include <runtime_svc.h> |
Caesar Wang | a845690 | 2016-10-27 01:12:34 +0800 | [diff] [blame] | 13 | #include <dfs.h> |
Caesar Wang | 9740bba | 2016-08-25 08:37:42 +0800 | [diff] [blame] | 14 | |
Caesar Wang | 251a34d | 2016-09-10 06:25:29 +0800 | [diff] [blame] | 15 | #define RK_SIP_DDR_CFG 0x82000008 |
| 16 | #define DRAM_INIT 0x00 |
| 17 | #define DRAM_SET_RATE 0x01 |
| 18 | #define DRAM_ROUND_RATE 0x02 |
| 19 | #define DRAM_SET_AT_SR 0x03 |
| 20 | #define DRAM_GET_BW 0x04 |
| 21 | #define DRAM_GET_RATE 0x05 |
| 22 | #define DRAM_CLR_IRQ 0x06 |
| 23 | #define DRAM_SET_PARAM 0x07 |
Derek Basehore | ff461d0 | 2016-10-20 20:46:43 -0700 | [diff] [blame] | 24 | #define DRAM_SET_ODT_PD 0x08 |
Caesar Wang | 9740bba | 2016-08-25 08:37:42 +0800 | [diff] [blame] | 25 | |
Ziyuan Xu | 4060cfd | 2017-02-10 11:54:52 +0800 | [diff] [blame] | 26 | #define RK_SIP_HDCP_CONTROL 0x82000009 |
| 27 | #define RK_SIP_HDCP_KEY_DATA64 0xC200000A |
| 28 | |
Derek Basehore | ff461d0 | 2016-10-20 20:46:43 -0700 | [diff] [blame] | 29 | uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, |
| 30 | uint64_t id, uint64_t arg2) |
Caesar Wang | 9740bba | 2016-08-25 08:37:42 +0800 | [diff] [blame] | 31 | { |
| 32 | switch (id) { |
Caesar Wang | 251a34d | 2016-09-10 06:25:29 +0800 | [diff] [blame] | 33 | case DRAM_SET_RATE: |
| 34 | return ddr_set_rate((uint32_t)arg0); |
| 35 | case DRAM_ROUND_RATE: |
| 36 | return ddr_round_rate((uint32_t)arg0); |
| 37 | case DRAM_GET_RATE: |
Caesar Wang | 9740bba | 2016-08-25 08:37:42 +0800 | [diff] [blame] | 38 | return ddr_get_rate(); |
Derek Basehore | ff461d0 | 2016-10-20 20:46:43 -0700 | [diff] [blame] | 39 | case DRAM_SET_ODT_PD: |
| 40 | dram_set_odt_pd(arg0, arg1, arg2); |
Caesar Wang | 9740bba | 2016-08-25 08:37:42 +0800 | [diff] [blame] | 41 | break; |
| 42 | default: |
| 43 | break; |
| 44 | } |
| 45 | |
| 46 | return 0; |
| 47 | } |
Caesar Wang | c1bf646 | 2016-06-21 14:44:01 +0800 | [diff] [blame] | 48 | |
| 49 | uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, |
| 50 | uint64_t x1, |
| 51 | uint64_t x2, |
| 52 | uint64_t x3, |
| 53 | uint64_t x4, |
| 54 | void *cookie, |
| 55 | void *handle, |
| 56 | uint64_t flags) |
| 57 | { |
Ziyuan Xu | 4060cfd | 2017-02-10 11:54:52 +0800 | [diff] [blame] | 58 | uint64_t x5, x6; |
| 59 | |
Caesar Wang | c1bf646 | 2016-06-21 14:44:01 +0800 | [diff] [blame] | 60 | switch (smc_fid) { |
Caesar Wang | 251a34d | 2016-09-10 06:25:29 +0800 | [diff] [blame] | 61 | case RK_SIP_DDR_CFG: |
Derek Basehore | ff461d0 | 2016-10-20 20:46:43 -0700 | [diff] [blame] | 62 | SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4)); |
Ziyuan Xu | 4060cfd | 2017-02-10 11:54:52 +0800 | [diff] [blame] | 63 | case RK_SIP_HDCP_CONTROL: |
| 64 | SMC_RET1(handle, dp_hdcp_ctrl(x1)); |
| 65 | case RK_SIP_HDCP_KEY_DATA64: |
| 66 | x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); |
| 67 | x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6); |
| 68 | SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6)); |
Caesar Wang | c1bf646 | 2016-06-21 14:44:01 +0800 | [diff] [blame] | 69 | default: |
| 70 | ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); |
| 71 | SMC_RET1(handle, SMC_UNK); |
| 72 | } |
| 73 | } |