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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekar952a5552018-02-13 20:22:19 -08002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
kalyani chidambaramca4e4972018-06-19 13:34:39 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05306 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00008#ifndef PMC_H
9#define PMC_H
Varun Wadekarb316e242015-05-19 16:48:04 +053010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/mmio.h>
12#include <lib/utils_def.h>
Varun Wadekar952a5552018-02-13 20:22:19 -080013#include <stdbool.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014
Varun Wadekarb316e242015-05-19 16:48:04 +053015#include <tegra_def.h>
16
Anthony Zhouc33c1e32017-03-13 16:47:58 +080017#define PMC_CONFIG U(0x0)
kalyani chidambaramb3873aa2018-04-09 14:40:02 -070018#define PMC_IO_DPD_SAMPLE U(0x20)
kalyani chidambarama1ad9b72018-03-06 16:36:57 -080019#define PMC_DPD_ENABLE_0 U(0x24)
Anthony Zhouc33c1e32017-03-13 16:47:58 +080020#define PMC_PWRGATE_STATUS U(0x38)
21#define PMC_PWRGATE_TOGGLE U(0x30)
kalyani chidambaramca4e4972018-06-19 13:34:39 -070022#define PMC_SCRATCH1 U(0x54)
kalyani chidambarama1ad9b72018-03-06 16:36:57 -080023#define PMC_CRYPTO_OP_0 U(0xf4)
Anthony Zhouc33c1e32017-03-13 16:47:58 +080024#define PMC_TOGGLE_START U(0x100)
kalyani chidambaramca4e4972018-06-19 13:34:39 -070025#define PMC_SCRATCH31 U(0x118)
26#define PMC_SCRATCH32 U(0x11C)
27#define PMC_SCRATCH33 U(0x120)
Anthony Zhouc33c1e32017-03-13 16:47:58 +080028#define PMC_SCRATCH39 U(0x138)
kalyani chidambaramca4e4972018-06-19 13:34:39 -070029#define PMC_SCRATCH40 U(0x13C)
kalyani chidambaramb3873aa2018-04-09 14:40:02 -070030#define PMC_SCRATCH41 U(0x140)
kalyani chidambaramca4e4972018-06-19 13:34:39 -070031#define PMC_SCRATCH42 U(0x144)
32#define PMC_SCRATCH43 U(0x22C)
33#define PMC_SCRATCH44 U(0x230)
34#define PMC_SCRATCH45 U(0x234)
35#define PMC_SCRATCH46 U(0x238)
36#define PMC_SCRATCH47 U(0x23C)
37#define PMC_SCRATCH48 U(0x240)
38#define PMC_SCRATCH50 U(0x248)
39#define PMC_SCRATCH51 U(0x24C)
40#define PMC_TSC_MULT_0 U(0x2B4)
41#define PMC_STICKY_BIT U(0x2C0)
42#define PMC_SECURE_DISABLE2 U(0x2C4)
Anthony Zhouc33c1e32017-03-13 16:47:58 +080043#define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28)
kalyani chidambarama1ad9b72018-03-06 16:36:57 -080044#define PMC_FUSE_CONTROL_0 U(0x450)
kalyani chidambaramca4e4972018-06-19 13:34:39 -070045#define PMC_SECURE_DISABLE3 U(0x2D8)
Anthony Zhouc33c1e32017-03-13 16:47:58 +080046#define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20)
47#define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22)
kalyani chidambaramca4e4972018-06-19 13:34:39 -070048#define PMC_SECURE_SCRATCH22 U(0x338)
Anthony Zhouc33c1e32017-03-13 16:47:58 +080049#define PMC_SECURE_SCRATCH34 U(0x368)
50#define PMC_SECURE_SCRATCH35 U(0x36c)
kalyani chidambaramca4e4972018-06-19 13:34:39 -070051#define PMC_SCRATCH56 U(0x600)
52#define PMC_SCRATCH57 U(0x604)
Varun Wadekarf07d6de2018-02-27 14:33:57 -080053#define PMC_SCRATCH201 U(0x844)
Varun Wadekarb316e242015-05-19 16:48:04 +053054
55static inline uint32_t tegra_pmc_read_32(uint32_t off)
56{
57 return mmio_read_32(TEGRA_PMC_BASE + off);
58}
59
60static inline void tegra_pmc_write_32(uint32_t off, uint32_t val)
61{
62 mmio_write_32(TEGRA_PMC_BASE + off, val);
63}
64
Varun Wadekar952a5552018-02-13 20:22:19 -080065void tegra_pmc_cpu_on(int32_t cpu);
Varun Wadekarb316e242015-05-19 16:48:04 +053066void tegra_pmc_cpu_setup(uint64_t reset_addr);
Varun Wadekar952a5552018-02-13 20:22:19 -080067bool tegra_pmc_is_last_on_cpu(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053068void tegra_pmc_lock_cpu_vectors(void);
kalyani chidambaramb3873aa2018-04-09 14:40:02 -070069void tegra_pmc_resume(void);
Varun Wadekarb316e242015-05-19 16:48:04 +053070__dead2 void tegra_pmc_system_reset(void);
71
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000072#endif /* PMC_H */