fdts/stm32mp131.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
 */
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/stm32mp13-resets.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clocks = <&rcc CK_MPU>;
			clock-names = "cpu";
			nvmem-cells = <&part_number_otp>;
			nvmem-cell-names = "part_number";
		};
	};

	clocks {
		clk_csi: clk-csi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <4000000>;
		};

		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};
	};

	intc: interrupt-controller@a0021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xa0021000 0x1000>,
		      <0xa0022000 0x2000>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		usart3: serial@4000f000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4000f000 0x400>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART3_K>;
			resets = <&rcc USART3_R>;
			status = "disabled";
		};

		uart4: serial@40010000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40010000 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART4_K>;
			resets = <&rcc UART4_R>;
			status = "disabled";
		};

		uart5: serial@40011000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40011000 0x400>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART5_K>;
			resets = <&rcc UART5_R>;
			status = "disabled";
		};

		uart7: serial@40018000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40018000 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART7_K>;
			resets = <&rcc UART7_R>;
			status = "disabled";
		};

		uart8: serial@40019000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40019000 0x400>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART8_K>;
			resets = <&rcc UART8_R>;
			status = "disabled";
		};

		usart6: serial@44003000 {
			compatible = "st,stm32h7-uart";
			reg = <0x44003000 0x400>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART6_K>;
			resets = <&rcc USART6_R>;
			status = "disabled";
		};

		usbotg_hs: usb-otg@49000000 {
			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
			reg = <0x49000000 0x40000>;
			clocks = <&rcc USBO_K>;
			clock-names = "otg";
			resets = <&rcc USBO_R>;
			reset-names = "dwc2";
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			g-rx-fifo-size = <512>;
			g-np-tx-fifo-size = <32>;
			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
			dr_mode = "otg";
			usb33d-supply = <&usb33>;
			status = "disabled";
		};

		usart1: serial@4c000000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4c000000 0x400>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART1_K>;
			resets = <&rcc USART1_R>;
			status = "disabled";
		};

		usart2: serial@4c001000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4c001000 0x400>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART2_K>;
			resets = <&rcc USART2_R>;
			status = "disabled";
		};

		i2c3: i2c@4c004000 {
			compatible = "st,stm32mp13-i2c";
			reg = <0x4c004000 0x400>;
			interrupt-names = "event", "error";
			interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C3_K>;
			resets = <&rcc I2C3_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			st,syscfg-fmp = <&syscfg 0x4 0x4>;
			i2c-analog-filter;
			status = "disabled";
		};

		i2c4: i2c@4c005000 {
			compatible = "st,stm32mp13-i2c";
			reg = <0x4c005000 0x400>;
			interrupt-names = "event", "error";
			interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C4_K>;
			resets = <&rcc I2C4_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			st,syscfg-fmp = <&syscfg 0x4 0x8>;
			i2c-analog-filter;
			status = "disabled";
		};

		i2c5: i2c@4c006000 {
			compatible = "st,stm32mp13-i2c";
			reg = <0x4c006000 0x400>;
			interrupt-names = "event", "error";
			interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C5_K>;
			resets = <&rcc I2C5_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			st,syscfg-fmp = <&syscfg 0x4 0x10>;
			i2c-analog-filter;
			status = "disabled";
		};

		rcc: rcc@50000000 {
			compatible = "st,stm32mp13-rcc", "syscon";
			reg = <0x50000000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			secure-interrupt-names = "wakeup";
		};

		pwr_regulators: pwr@50001000 {
			compatible = "st,stm32mp1,pwr-reg";
			reg = <0x50001000 0x10>;

			reg11: reg11 {
				regulator-name = "reg11";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
			};

			reg18: reg18 {
				regulator-name = "reg18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			usb33: usb33 {
				regulator-name = "usb33";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};
		};

		exti: interrupt-controller@5000d000 {
			compatible = "st,stm32mp13-exti", "syscon";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x5000d000 0x400>;
		};

		syscfg: syscon@50020000 {
			compatible = "st,stm32mp157-syscfg", "syscon";
			reg = <0x50020000 0x400>;
			clocks = <&rcc SYSCFG>;
		};

		hash: hash@54003000 {
			compatible = "st,stm32mp13-hash";
			reg = <0x54003000 0x400>;
			clocks = <&rcc HASH1>;
			resets = <&rcc HASH1_R>;
			status = "disabled";
		};

		rng: rng@54004000 {
			compatible = "st,stm32mp13-rng";
			reg = <0x54004000 0x400>;
			clocks = <&rcc RNG1_K>;
			resets = <&rcc RNG1_R>;
			status = "disabled";
		};

		fmc: memory-controller@58002000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "st,stm32mp1-fmc2-ebi";
			reg = <0x58002000 0x1000>;
			clocks = <&rcc FMC_K>;
			resets = <&rcc FMC_R>;
			status = "disabled";

			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
				 <4 0 0x80000000 0x10000000>; /* NAND */

			nand-controller@4,0 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp1-fmc2-nfc";
				reg = <4 0x00000000 0x1000>,
				      <4 0x08010000 0x1000>,
				      <4 0x08020000 0x1000>,
				      <4 0x01000000 0x1000>,
				      <4 0x09010000 0x1000>,
				      <4 0x09020000 0x1000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
		};

		qspi: spi@58003000 {
			compatible = "st,stm32f469-qspi";
			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
			reg-names = "qspi", "qspi_mm";
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc QSPI_K>;
			resets = <&rcc QSPI_R>;
			status = "disabled";
		};

		sdmmc1: mmc@58005000 {
			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x20253180>;
			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
			clocks = <&rcc SDMMC1_K>;
			clock-names = "apb_pclk";
			resets = <&rcc SDMMC1_R>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <130000000>;
			status = "disabled";
		};

		sdmmc2: mmc@58007000 {
			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x20253180>;
			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
			clocks = <&rcc SDMMC2_K>;
			clock-names = "apb_pclk";
			resets = <&rcc SDMMC2_R>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <130000000>;
			status = "disabled";
		};

		usbh_ohci: usbh-ohci@5800c000 {
			compatible = "generic-ohci";
			reg = <0x5800c000 0x1000>;
			clocks = <&rcc USBH>;
			resets = <&rcc USBH_R>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		usbh_ehci: usbh-ehci@5800d000 {
			compatible = "generic-ehci";
			reg = <0x5800d000 0x1000>;
			clocks = <&rcc USBH>;
			resets = <&rcc USBH_R>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			companion = <&usbh_ohci>;
			status = "disabled";
		};

		iwdg2: watchdog@5a002000 {
			compatible = "st,stm32mp1-iwdg";
			reg = <0x5a002000 0x400>;
			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
			clock-names = "pclk", "lsi";
			status = "disabled";
		};

		ddr: ddr@5a003000 {
			compatible = "st,stm32mp13-ddr";
			reg = <0x5a003000 0x550>, <0x5a004000 0x234>;
			clocks = <&rcc AXIDCG>,
				 <&rcc DDRC1>,
				 <&rcc DDRPHYC>,
				 <&rcc DDRCAPB>,
				 <&rcc DDRPHYCAPB>;
			clock-names = "axidcg",
				      "ddrc1",
				      "ddrphyc",
				      "ddrcapb",
				      "ddrphycapb";
		};

		usbphyc: usbphyc@5a006000 {
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <0>;
			compatible = "st,stm32mp1-usbphyc";
			reg = <0x5a006000 0x1000>;
			clocks = <&rcc USBPHY_K>;
			resets = <&rcc USBPHY_R>;
			vdda1v1-supply = <&reg11>;
			vdda1v8-supply = <&reg18>;
			status = "disabled";

			usbphyc_port0: usb-phy@0 {
				#phy-cells = <0>;
				reg = <0>;
			};

			usbphyc_port1: usb-phy@1 {
				#phy-cells = <1>;
				reg = <1>;
			};
		};

		iwdg1: watchdog@5c003000 {
			compatible = "st,stm32mp1-iwdg";
			reg = <0x5c003000 0x400>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
			clock-names = "pclk", "lsi";
			status = "disabled";
		};

		bsec: efuse@5c005000 {
			compatible = "st,stm32mp15-bsec";
			reg = <0x5c005000 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;

			cfg0_otp: cfg0_otp@0 {
				reg = <0x0 0x2>;
			};
			part_number_otp: part_number_otp@4 {
				reg = <0x4 0x2>;
			};
			monotonic_otp: monotonic_otp@10 {
				reg = <0x10 0x4>;
			};
			nand_otp: cfg9_otp@24 {
				reg = <0x24 0x4>;
			};
			nand2_otp: cfg10_otp@28 {
				reg = <0x28 0x4>;
			};
			uid_otp: uid_otp@34 {
				reg = <0x34 0xc>;
			};
			hw2_otp: hw2_otp@48 {
				reg = <0x48 0x4>;
			};
			ts_cal1: calib@5c {
				reg = <0x5c 0x2>;
			};
			ts_cal2: calib@5e {
				reg = <0x5e 0x2>;
			};
			pkh_otp: pkh_otp@60 {
				reg = <0x60 0x20>;
			};
			mac_addr: mac_addr@e4 {
				reg = <0xe4 0xc>;
				st,non-secure-otp;
			};
			enckey_otp: enckey_otp@170 {
				reg = <0x170 0x10>;
			};
		};
		/*
		 * Break node order to solve dependency probe issue between
		 * pinctrl and exti.
		 */
		pinctrl: pinctrl@50002000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp135-pinctrl";
			ranges = <0 0x50002000 0x8400>;
			interrupt-parent = <&exti>;
			st,syscfg = <&exti 0x60 0xff>;
			pins-are-numbered;

			gpioa: gpio@50002000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc GPIOA>;
				st,bank-name = "GPIOA";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 0 16>;
			};

			gpiob: gpio@50003000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc GPIOB>;
				st,bank-name = "GPIOB";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 16 16>;
			};

			gpioc: gpio@50004000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc GPIOC>;
				st,bank-name = "GPIOC";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 32 16>;
			};

			gpiod: gpio@50005000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x3000 0x400>;
				clocks = <&rcc GPIOD>;
				st,bank-name = "GPIOD";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 48 16>;
			};

			gpioe: gpio@50006000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x4000 0x400>;
				clocks = <&rcc GPIOE>;
				st,bank-name = "GPIOE";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 64 16>;
			};

			gpiof: gpio@50007000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x5000 0x400>;
				clocks = <&rcc GPIOF>;
				st,bank-name = "GPIOF";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 80 16>;
			};

			gpiog: gpio@50008000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x6000 0x400>;
				clocks = <&rcc GPIOG>;
				st,bank-name = "GPIOG";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 96 16>;
			};

			gpioh: gpio@50009000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x7000 0x400>;
				clocks = <&rcc GPIOH>;
				st,bank-name = "GPIOH";
				ngpios = <15>;
				gpio-ranges = <&pinctrl 0 112 15>;
			};

			gpioi: gpio@5000a000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x8000 0x400>;
				clocks = <&rcc GPIOI>;
				st,bank-name = "GPIOI";
				ngpios = <8>;
				gpio-ranges = <&pinctrl 0 128 8>;
			};
		};
	};
};