Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/debug.h> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 10 | #include <cortex_a57.h> |
| 11 | #include <cpu_macros.S> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable intra-cluster coherency |
| 15 | * Clobbers: r0-r1 |
| 16 | * --------------------------------------------- |
| 17 | */ |
| 18 | func cortex_a57_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 19 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 20 | bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT |
| 21 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 22 | bx lr |
| 23 | endfunc cortex_a57_disable_smp |
| 24 | |
| 25 | /* --------------------------------------------- |
| 26 | * Disable all types of L2 prefetches. |
| 27 | * Clobbers: r0-r2 |
| 28 | * --------------------------------------------- |
| 29 | */ |
| 30 | func cortex_a57_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 31 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 32 | orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 33 | bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \ |
| 34 | CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK) |
| 35 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 36 | isb |
| 37 | dsb ish |
| 38 | bx lr |
| 39 | endfunc cortex_a57_disable_l2_prefetch |
| 40 | |
| 41 | /* --------------------------------------------- |
| 42 | * Disable debug interfaces |
| 43 | * --------------------------------------------- |
| 44 | */ |
| 45 | func cortex_a57_disable_ext_debug |
| 46 | mov r0, #1 |
| 47 | stcopr r0, DBGOSDLR |
| 48 | isb |
| 49 | dsb sy |
| 50 | bx lr |
| 51 | endfunc cortex_a57_disable_ext_debug |
| 52 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 53 | /* -------------------------------------------------- |
| 54 | * Errata Workaround for Cortex A57 Errata #806969. |
| 55 | * This applies only to revision r0p0 of Cortex A57. |
| 56 | * Inputs: |
| 57 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 58 | * Shall clobber: r0-r3 |
| 59 | * -------------------------------------------------- |
| 60 | */ |
| 61 | func errata_a57_806969_wa |
| 62 | /* |
| 63 | * Compare r0 against revision r0p0 |
| 64 | */ |
| 65 | mov r2, lr |
| 66 | bl check_errata_806969 |
| 67 | mov lr, r2 |
| 68 | cmp r0, #ERRATA_NOT_APPLIES |
| 69 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 70 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 71 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA |
| 72 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 73 | 1: |
| 74 | bx lr |
| 75 | endfunc errata_a57_806969_wa |
| 76 | |
| 77 | func check_errata_806969 |
| 78 | mov r1, #0x00 |
| 79 | b cpu_rev_var_ls |
| 80 | endfunc check_errata_806969 |
| 81 | |
| 82 | /* --------------------------------------------------- |
| 83 | * Errata Workaround for Cortex A57 Errata #813419. |
| 84 | * This applies only to revision r0p0 of Cortex A57. |
| 85 | * --------------------------------------------------- |
| 86 | */ |
| 87 | func check_errata_813419 |
| 88 | /* |
| 89 | * Even though this is only needed for revision r0p0, it |
| 90 | * is always applied due to limitations of the current |
| 91 | * errata framework. |
| 92 | */ |
| 93 | mov r0, #ERRATA_APPLIES |
| 94 | bx lr |
| 95 | endfunc check_errata_813419 |
| 96 | |
| 97 | /* --------------------------------------------------- |
| 98 | * Errata Workaround for Cortex A57 Errata #813420. |
| 99 | * This applies only to revision r0p0 of Cortex A57. |
| 100 | * Inputs: |
| 101 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 102 | * Shall clobber: r0-r3 |
| 103 | * --------------------------------------------------- |
| 104 | */ |
| 105 | func errata_a57_813420_wa |
| 106 | /* |
| 107 | * Compare r0 against revision r0p0 |
| 108 | */ |
| 109 | mov r2, lr |
| 110 | bl check_errata_813420 |
| 111 | mov lr, r2 |
| 112 | cmp r0, #ERRATA_NOT_APPLIES |
| 113 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 114 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 115 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI |
| 116 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 117 | 1: |
| 118 | bx lr |
| 119 | endfunc errata_a57_813420_wa |
| 120 | |
| 121 | func check_errata_813420 |
| 122 | mov r1, #0x00 |
| 123 | b cpu_rev_var_ls |
| 124 | endfunc check_errata_813420 |
| 125 | |
| 126 | /* -------------------------------------------------------------------- |
| 127 | * Disable the over-read from the LDNP instruction. |
| 128 | * |
| 129 | * This applies to all revisions <= r1p2. The performance degradation |
| 130 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 131 | * |
| 132 | * Inputs: |
| 133 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 134 | * Shall clobber: r0-r3 |
| 135 | * --------------------------------------------------------------------- |
| 136 | */ |
| 137 | func a57_disable_ldnp_overread |
| 138 | /* |
| 139 | * Compare r0 against revision r1p2 |
| 140 | */ |
| 141 | mov r2, lr |
| 142 | bl check_errata_disable_ldnp_overread |
| 143 | mov lr, r2 |
| 144 | cmp r0, #ERRATA_NOT_APPLIES |
| 145 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 146 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 147 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD |
| 148 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 149 | 1: |
| 150 | bx lr |
| 151 | endfunc a57_disable_ldnp_overread |
| 152 | |
| 153 | func check_errata_disable_ldnp_overread |
| 154 | mov r1, #0x12 |
| 155 | b cpu_rev_var_ls |
| 156 | endfunc check_errata_disable_ldnp_overread |
| 157 | |
| 158 | /* --------------------------------------------------- |
| 159 | * Errata Workaround for Cortex A57 Errata #826974. |
| 160 | * This applies only to revision <= r1p1 of Cortex A57. |
| 161 | * Inputs: |
| 162 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 163 | * Shall clobber: r0-r3 |
| 164 | * --------------------------------------------------- |
| 165 | */ |
| 166 | func errata_a57_826974_wa |
| 167 | /* |
| 168 | * Compare r0 against revision r1p1 |
| 169 | */ |
| 170 | mov r2, lr |
| 171 | bl check_errata_826974 |
| 172 | mov lr, r2 |
| 173 | cmp r0, #ERRATA_NOT_APPLIES |
| 174 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 175 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 176 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB |
| 177 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 178 | 1: |
| 179 | bx lr |
| 180 | endfunc errata_a57_826974_wa |
| 181 | |
| 182 | func check_errata_826974 |
| 183 | mov r1, #0x11 |
| 184 | b cpu_rev_var_ls |
| 185 | endfunc check_errata_826974 |
| 186 | |
| 187 | /* --------------------------------------------------- |
| 188 | * Errata Workaround for Cortex A57 Errata #826977. |
| 189 | * This applies only to revision <= r1p1 of Cortex A57. |
| 190 | * Inputs: |
| 191 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 192 | * Shall clobber: r0-r3 |
| 193 | * --------------------------------------------------- |
| 194 | */ |
| 195 | func errata_a57_826977_wa |
| 196 | /* |
| 197 | * Compare r0 against revision r1p1 |
| 198 | */ |
| 199 | mov r2, lr |
| 200 | bl check_errata_826977 |
| 201 | mov lr, r2 |
| 202 | cmp r0, #ERRATA_NOT_APPLIES |
| 203 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 204 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 205 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE |
| 206 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 207 | 1: |
| 208 | bx lr |
| 209 | endfunc errata_a57_826977_wa |
| 210 | |
| 211 | func check_errata_826977 |
| 212 | mov r1, #0x11 |
| 213 | b cpu_rev_var_ls |
| 214 | endfunc check_errata_826977 |
| 215 | |
| 216 | /* --------------------------------------------------- |
| 217 | * Errata Workaround for Cortex A57 Errata #828024. |
| 218 | * This applies only to revision <= r1p1 of Cortex A57. |
| 219 | * Inputs: |
| 220 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 221 | * Shall clobber: r0-r3 |
| 222 | * --------------------------------------------------- |
| 223 | */ |
| 224 | func errata_a57_828024_wa |
| 225 | /* |
| 226 | * Compare r0 against revision r1p1 |
| 227 | */ |
| 228 | mov r2, lr |
| 229 | bl check_errata_828024 |
| 230 | mov lr, r2 |
| 231 | cmp r0, #ERRATA_NOT_APPLIES |
| 232 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 233 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 234 | /* |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 235 | * Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2 |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 236 | * instructions here because the resulting bitmask doesn't fit in a |
| 237 | * 16-bit value so it cannot be encoded in a single instruction. |
| 238 | */ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 239 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA |
| 240 | orr64_imm r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING) |
| 241 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 242 | 1: |
| 243 | bx lr |
| 244 | endfunc errata_a57_828024_wa |
| 245 | |
| 246 | func check_errata_828024 |
| 247 | mov r1, #0x11 |
| 248 | b cpu_rev_var_ls |
| 249 | endfunc check_errata_828024 |
| 250 | |
| 251 | /* --------------------------------------------------- |
| 252 | * Errata Workaround for Cortex A57 Errata #829520. |
| 253 | * This applies only to revision <= r1p2 of Cortex A57. |
| 254 | * Inputs: |
| 255 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 256 | * Shall clobber: r0-r3 |
| 257 | * --------------------------------------------------- |
| 258 | */ |
| 259 | func errata_a57_829520_wa |
| 260 | /* |
| 261 | * Compare r0 against revision r1p2 |
| 262 | */ |
| 263 | mov r2, lr |
| 264 | bl check_errata_829520 |
| 265 | mov lr, r2 |
| 266 | cmp r0, #ERRATA_NOT_APPLIES |
| 267 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 268 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 269 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR |
| 270 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 271 | 1: |
| 272 | bx lr |
| 273 | endfunc errata_a57_829520_wa |
| 274 | |
| 275 | func check_errata_829520 |
| 276 | mov r1, #0x12 |
| 277 | b cpu_rev_var_ls |
| 278 | endfunc check_errata_829520 |
| 279 | |
| 280 | /* --------------------------------------------------- |
| 281 | * Errata Workaround for Cortex A57 Errata #833471. |
| 282 | * This applies only to revision <= r1p2 of Cortex A57. |
| 283 | * Inputs: |
| 284 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 285 | * Shall clobber: r0-r3 |
| 286 | * --------------------------------------------------- |
| 287 | */ |
| 288 | func errata_a57_833471_wa |
| 289 | /* |
| 290 | * Compare r0 against revision r1p2 |
| 291 | */ |
| 292 | mov r2, lr |
| 293 | bl check_errata_833471 |
| 294 | mov lr, r2 |
| 295 | cmp r0, #ERRATA_NOT_APPLIES |
| 296 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 297 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 298 | orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH |
| 299 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 300 | 1: |
| 301 | bx lr |
| 302 | endfunc errata_a57_833471_wa |
| 303 | |
| 304 | func check_errata_833471 |
| 305 | mov r1, #0x12 |
| 306 | b cpu_rev_var_ls |
| 307 | endfunc check_errata_833471 |
| 308 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 309 | /* --------------------------------------------------- |
| 310 | * Errata Workaround for Cortex A57 Errata #859972. |
| 311 | * This applies only to revision <= r1p3 of Cortex A57. |
| 312 | * Inputs: |
| 313 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 314 | * Shall clobber: r0-r3 |
| 315 | * --------------------------------------------------- |
| 316 | */ |
| 317 | func errata_a57_859972_wa |
| 318 | mov r2, lr |
| 319 | bl check_errata_859972 |
| 320 | mov lr, r2 |
| 321 | cmp r0, #ERRATA_NOT_APPLIES |
| 322 | beq 1f |
| 323 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 324 | orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH |
| 325 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 326 | 1: |
| 327 | bx lr |
| 328 | endfunc errata_a57_859972_wa |
| 329 | |
| 330 | func check_errata_859972 |
| 331 | mov r1, #0x13 |
| 332 | b cpu_rev_var_ls |
| 333 | endfunc check_errata_859972 |
| 334 | |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 335 | func check_errata_cve_2017_5715 |
| 336 | mov r0, #ERRATA_MISSING |
| 337 | bx lr |
| 338 | endfunc check_errata_cve_2017_5715 |
| 339 | |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 340 | func check_errata_cve_2018_3639 |
| 341 | #if WORKAROUND_CVE_2018_3639 |
| 342 | mov r0, #ERRATA_APPLIES |
| 343 | #else |
| 344 | mov r0, #ERRATA_MISSING |
| 345 | #endif |
| 346 | bx lr |
| 347 | endfunc check_errata_cve_2018_3639 |
| 348 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 349 | /* ------------------------------------------------- |
| 350 | * The CPU Ops reset function for Cortex-A57. |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 351 | * Shall clobber: r0-r6 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 352 | * ------------------------------------------------- |
| 353 | */ |
| 354 | func cortex_a57_reset_func |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 355 | mov r5, lr |
| 356 | bl cpu_get_rev_var |
| 357 | mov r4, r0 |
| 358 | |
| 359 | #if ERRATA_A57_806969 |
| 360 | mov r0, r4 |
| 361 | bl errata_a57_806969_wa |
| 362 | #endif |
| 363 | |
| 364 | #if ERRATA_A57_813420 |
| 365 | mov r0, r4 |
| 366 | bl errata_a57_813420_wa |
| 367 | #endif |
| 368 | |
| 369 | #if A57_DISABLE_NON_TEMPORAL_HINT |
| 370 | mov r0, r4 |
| 371 | bl a57_disable_ldnp_overread |
| 372 | #endif |
| 373 | |
| 374 | #if ERRATA_A57_826974 |
| 375 | mov r0, r4 |
| 376 | bl errata_a57_826974_wa |
| 377 | #endif |
| 378 | |
| 379 | #if ERRATA_A57_826977 |
| 380 | mov r0, r4 |
| 381 | bl errata_a57_826977_wa |
| 382 | #endif |
| 383 | |
| 384 | #if ERRATA_A57_828024 |
| 385 | mov r0, r4 |
| 386 | bl errata_a57_828024_wa |
| 387 | #endif |
| 388 | |
| 389 | #if ERRATA_A57_829520 |
| 390 | mov r0, r4 |
| 391 | bl errata_a57_829520_wa |
| 392 | #endif |
| 393 | |
| 394 | #if ERRATA_A57_833471 |
| 395 | mov r0, r4 |
| 396 | bl errata_a57_833471_wa |
| 397 | #endif |
| 398 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 399 | #if ERRATA_A57_859972 |
| 400 | mov r0, r4 |
| 401 | bl errata_a57_859972_wa |
| 402 | #endif |
| 403 | |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 404 | #if WORKAROUND_CVE_2018_3639 |
| 405 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 406 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE |
| 407 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 408 | isb |
| 409 | dsb sy |
| 410 | #endif |
| 411 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 412 | /* --------------------------------------------- |
| 413 | * Enable the SMP bit. |
| 414 | * --------------------------------------------- |
| 415 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 416 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 417 | orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT |
| 418 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 419 | isb |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 420 | bx r5 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 421 | endfunc cortex_a57_reset_func |
| 422 | |
| 423 | /* ---------------------------------------------------- |
| 424 | * The CPU Ops core power down function for Cortex-A57. |
| 425 | * ---------------------------------------------------- |
| 426 | */ |
| 427 | func cortex_a57_core_pwr_dwn |
| 428 | push {r12, lr} |
| 429 | |
| 430 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 431 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 432 | ldcopr r0, SCTLR |
| 433 | tst r0, #SCTLR_C_BIT |
| 434 | ASM_ASSERT(eq) |
| 435 | #endif |
| 436 | |
| 437 | /* --------------------------------------------- |
| 438 | * Disable the L2 prefetches. |
| 439 | * --------------------------------------------- |
| 440 | */ |
| 441 | bl cortex_a57_disable_l2_prefetch |
| 442 | |
| 443 | /* --------------------------------------------- |
| 444 | * Flush L1 caches. |
| 445 | * --------------------------------------------- |
| 446 | */ |
| 447 | mov r0, #DC_OP_CISW |
| 448 | bl dcsw_op_level1 |
| 449 | |
| 450 | /* --------------------------------------------- |
| 451 | * Come out of intra cluster coherency |
| 452 | * --------------------------------------------- |
| 453 | */ |
| 454 | bl cortex_a57_disable_smp |
| 455 | |
| 456 | /* --------------------------------------------- |
| 457 | * Force the debug interfaces to be quiescent |
| 458 | * --------------------------------------------- |
| 459 | */ |
| 460 | pop {r12, lr} |
| 461 | b cortex_a57_disable_ext_debug |
| 462 | endfunc cortex_a57_core_pwr_dwn |
| 463 | |
| 464 | /* ------------------------------------------------------- |
| 465 | * The CPU Ops cluster power down function for Cortex-A57. |
| 466 | * Clobbers: r0-r3 |
| 467 | * ------------------------------------------------------- |
| 468 | */ |
| 469 | func cortex_a57_cluster_pwr_dwn |
| 470 | push {r12, lr} |
| 471 | |
| 472 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 473 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 474 | ldcopr r0, SCTLR |
| 475 | tst r0, #SCTLR_C_BIT |
| 476 | ASM_ASSERT(eq) |
| 477 | #endif |
| 478 | |
| 479 | /* --------------------------------------------- |
| 480 | * Disable the L2 prefetches. |
| 481 | * --------------------------------------------- |
| 482 | */ |
| 483 | bl cortex_a57_disable_l2_prefetch |
| 484 | |
| 485 | /* --------------------------------------------- |
| 486 | * Flush L1 caches. |
| 487 | * --------------------------------------------- |
| 488 | */ |
| 489 | mov r0, #DC_OP_CISW |
| 490 | bl dcsw_op_level1 |
| 491 | |
| 492 | /* --------------------------------------------- |
| 493 | * Disable the optional ACP. |
| 494 | * --------------------------------------------- |
| 495 | */ |
| 496 | bl plat_disable_acp |
| 497 | |
| 498 | /* --------------------------------------------- |
| 499 | * Flush L2 caches. |
| 500 | * --------------------------------------------- |
| 501 | */ |
| 502 | mov r0, #DC_OP_CISW |
| 503 | bl dcsw_op_level2 |
| 504 | |
| 505 | /* --------------------------------------------- |
| 506 | * Come out of intra cluster coherency |
| 507 | * --------------------------------------------- |
| 508 | */ |
| 509 | bl cortex_a57_disable_smp |
| 510 | |
| 511 | /* --------------------------------------------- |
| 512 | * Force the debug interfaces to be quiescent |
| 513 | * --------------------------------------------- |
| 514 | */ |
| 515 | pop {r12, lr} |
| 516 | b cortex_a57_disable_ext_debug |
| 517 | endfunc cortex_a57_cluster_pwr_dwn |
| 518 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 519 | #if REPORT_ERRATA |
| 520 | /* |
| 521 | * Errata printing function for Cortex A57. Must follow AAPCS. |
| 522 | */ |
| 523 | func cortex_a57_errata_report |
| 524 | push {r12, lr} |
| 525 | |
| 526 | bl cpu_get_rev_var |
| 527 | mov r4, r0 |
| 528 | |
| 529 | /* |
| 530 | * Report all errata. The revision-variant information is passed to |
| 531 | * checking functions of each errata. |
| 532 | */ |
| 533 | report_errata ERRATA_A57_806969, cortex_a57, 806969 |
| 534 | report_errata ERRATA_A57_813419, cortex_a57, 813419 |
| 535 | report_errata ERRATA_A57_813420, cortex_a57, 813420 |
| 536 | report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ |
| 537 | disable_ldnp_overread |
| 538 | report_errata ERRATA_A57_826974, cortex_a57, 826974 |
| 539 | report_errata ERRATA_A57_826977, cortex_a57, 826977 |
| 540 | report_errata ERRATA_A57_828024, cortex_a57, 828024 |
| 541 | report_errata ERRATA_A57_829520, cortex_a57, 829520 |
| 542 | report_errata ERRATA_A57_833471, cortex_a57, 833471 |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 543 | report_errata ERRATA_A57_859972, cortex_a57, 859972 |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 544 | report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 545 | report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 546 | |
| 547 | pop {r12, lr} |
| 548 | bx lr |
| 549 | endfunc cortex_a57_errata_report |
| 550 | #endif |
| 551 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 552 | declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ |
| 553 | cortex_a57_reset_func, \ |
| 554 | cortex_a57_core_pwr_dwn, \ |
| 555 | cortex_a57_cluster_pwr_dwn |