| Loh Tien Hock | 59400a4 | 2019-02-04 16:17:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef _HANDOFF_H_ |
| 8 | #define _HANDOFF_H_ |
| 9 | |
| 10 | #define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ |
| 11 | #define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ |
| 12 | #define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ |
| 13 | #define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ |
| 14 | #define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ |
| 15 | #define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ |
| 16 | #define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ |
| 17 | |
| 18 | typedef struct handoff_t { |
| 19 | /* header */ |
| 20 | uint32_t header_magic; |
| 21 | uint32_t header_device; |
| 22 | uint32_t _pad_0x08_0x10[2]; |
| 23 | |
| 24 | /* pinmux configuration - select */ |
| 25 | uint32_t pinmux_sel_magic; |
| 26 | uint32_t pinmux_sel_length; |
| 27 | uint32_t _pad_0x18_0x20[2]; |
| 28 | uint32_t pinmux_sel_array[96]; /* offset, value */ |
| 29 | |
| 30 | /* pinmux configuration - io control */ |
| 31 | uint32_t pinmux_io_magic; |
| 32 | uint32_t pinmux_io_length; |
| 33 | uint32_t _pad_0x1a8_0x1b0[2]; |
| 34 | uint32_t pinmux_io_array[96]; /* offset, value */ |
| 35 | |
| 36 | /* pinmux configuration - use fpga switch */ |
| 37 | uint32_t pinmux_fpga_magic; |
| 38 | uint32_t pinmux_fpga_length; |
| 39 | uint32_t _pad_0x338_0x340[2]; |
| 40 | uint32_t pinmux_fpga_array[42]; /* offset, value */ |
| 41 | uint32_t _pad_0x3e8_0x3f0[2]; |
| 42 | |
| 43 | /* pinmux configuration - io delay */ |
| 44 | uint32_t pinmux_delay_magic; |
| 45 | uint32_t pinmux_delay_length; |
| 46 | uint32_t _pad_0x3f8_0x400[2]; |
| 47 | uint32_t pinmux_iodelay_array[96]; /* offset, value */ |
| 48 | |
| 49 | /* clock configuration */ |
| 50 | uint32_t clock_magic; |
| 51 | uint32_t clock_length; |
| 52 | uint32_t _pad_0x588_0x590[2]; |
| 53 | uint32_t main_pll_mpuclk; |
| 54 | uint32_t main_pll_nocclk; |
| 55 | uint32_t main_pll_cntr2clk; |
| 56 | uint32_t main_pll_cntr3clk; |
| 57 | uint32_t main_pll_cntr4clk; |
| 58 | uint32_t main_pll_cntr5clk; |
| 59 | uint32_t main_pll_cntr6clk; |
| 60 | uint32_t main_pll_cntr7clk; |
| 61 | uint32_t main_pll_cntr8clk; |
| 62 | uint32_t main_pll_cntr9clk; |
| 63 | uint32_t main_pll_nocdiv; |
| 64 | uint32_t main_pll_pllglob; |
| 65 | uint32_t main_pll_fdbck; |
| 66 | uint32_t main_pll_pllc0; |
| 67 | uint32_t main_pll_pllc1; |
| 68 | uint32_t _pad_0x5cc_0x5d0[1]; |
| 69 | uint32_t per_pll_cntr2clk; |
| 70 | uint32_t per_pll_cntr3clk; |
| 71 | uint32_t per_pll_cntr4clk; |
| 72 | uint32_t per_pll_cntr5clk; |
| 73 | uint32_t per_pll_cntr6clk; |
| 74 | uint32_t per_pll_cntr7clk; |
| 75 | uint32_t per_pll_cntr8clk; |
| 76 | uint32_t per_pll_cntr9clk; |
| 77 | uint32_t per_pll_emacctl; |
| 78 | uint32_t per_pll_gpiodiv; |
| 79 | uint32_t per_pll_pllglob; |
| 80 | uint32_t per_pll_fdbck; |
| 81 | uint32_t per_pll_pllc0; |
| 82 | uint32_t per_pll_pllc1; |
| 83 | uint32_t hps_osc_clk_h; |
| 84 | uint32_t fpga_clk_hz; |
| 85 | |
| 86 | /* misc configuration */ |
| 87 | uint32_t misc_magic; |
| 88 | uint32_t misc_length; |
| 89 | uint32_t _pad_0x618_0x620[2]; |
| 90 | uint32_t boot_source; |
| 91 | } handoff; |
| 92 | |
| 93 | int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); |
| 94 | int s10_get_handoff(handoff *hoff_ptr); |
| 95 | |
| 96 | #endif |
| 97 | |
| 98 | |