| Andre Przywara | 452b2b6 | 2018-09-28 00:37:19 +0100 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | include lib/xlat_tables_v2/xlat_tables.mk |
| 8 | |
| 9 | AW_PLAT := plat/allwinner |
| 10 | |
| 11 | PLAT_INCLUDES := -Iinclude/plat/arm/common \ |
| 12 | -Iinclude/plat/arm/common/aarch64 \ |
| 13 | -I${AW_PLAT}/common/include \ |
| 14 | -I${AW_PLAT}/${PLAT}/include |
| 15 | |
| Andre Przywara | ea5fa47 | 2018-09-16 02:08:06 +0100 | [diff] [blame] | 16 | include lib/libfdt/libfdt.mk |
| 17 | |
| Julius Werner | 6b88b65 | 2018-11-27 17:50:28 -0800 | [diff] [blame] | 18 | PLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \ |
| Andre Przywara | 452b2b6 | 2018-09-28 00:37:19 +0100 | [diff] [blame] | 19 | ${XLAT_TABLES_LIB_SRCS} \ |
| 20 | ${AW_PLAT}/common/plat_helpers.S \ |
| 21 | ${AW_PLAT}/common/sunxi_common.c |
| 22 | |
| 23 | BL31_SOURCES += drivers/arm/gic/common/gic_common.c \ |
| 24 | drivers/arm/gic/v2/gicv2_helpers.c \ |
| 25 | drivers/arm/gic/v2/gicv2_main.c \ |
| 26 | drivers/delay_timer/delay_timer.c \ |
| 27 | drivers/delay_timer/generic_delay_timer.c \ |
| 28 | lib/cpus/${ARCH}/cortex_a53.S \ |
| 29 | plat/common/plat_gicv2.c \ |
| 30 | plat/common/plat_psci_common.c \ |
| 31 | ${AW_PLAT}/common/sunxi_bl31_setup.c \ |
| 32 | ${AW_PLAT}/common/sunxi_cpu_ops.c \ |
| 33 | ${AW_PLAT}/common/sunxi_pm.c \ |
| 34 | ${AW_PLAT}/${PLAT}/sunxi_power.c \ |
| 35 | ${AW_PLAT}/common/sunxi_security.c \ |
| 36 | ${AW_PLAT}/common/sunxi_topology.c |
| 37 | |
| 38 | # The bootloader is guaranteed to only run on CPU 0 by the boot ROM. |
| 39 | COLD_BOOT_SINGLE_CPU := 1 |
| 40 | |
| Samuel Holland | c47f00e | 2019-06-08 16:03:32 -0500 | [diff] [blame] | 41 | # Do not enable SPE (not supported on ARM v8.0). |
| 42 | ENABLE_SPE_FOR_LOWER_ELS := 0 |
| 43 | |
| 44 | # Do not enable SVE (not supported on ARM v8.0). |
| 45 | ENABLE_SVE_FOR_NS := 0 |
| 46 | |
| Andre Przywara | 452b2b6 | 2018-09-28 00:37:19 +0100 | [diff] [blame] | 47 | # Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4. |
| 48 | ERRATA_A53_835769 := 1 |
| 49 | ERRATA_A53_843419 := 1 |
| 50 | ERRATA_A53_855873 := 1 |
| 51 | |
| Andre Przywara | 452b2b6 | 2018-09-28 00:37:19 +0100 | [diff] [blame] | 52 | # The reset vector can be changed for each CPU. |
| 53 | PROGRAMMABLE_RESET_ADDRESS := 1 |
| 54 | |
| 55 | # Allow mapping read-only data as execute-never. |
| 56 | SEPARATE_CODE_AND_RODATA := 1 |
| 57 | |
| 58 | # BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL |
| 59 | RESET_TO_BL31 := 1 |
| Andre Przywara | 647a2e1 | 2018-10-11 22:14:30 +0100 | [diff] [blame] | 60 | |
| 61 | # We are short on memory, so save 3.5KB by not having an extra coherent page. |
| 62 | USE_COHERENT_MEM := 0 |
| Samuel Holland | c47f00e | 2019-06-08 16:03:32 -0500 | [diff] [blame] | 63 | |
| 64 | # This platform is single-cluster and does not require coherency setup. |
| 65 | WARMBOOT_ENABLE_DCACHE_EARLY := 1 |