| Olivier Deprez | 5ac897f | 2020-01-09 10:45:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | 5528325 | 2020-01-09 08:58:34 -0800 | [diff] [blame^] | 3 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
| Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| Varun Wadekar | 5528325 | 2020-01-09 08:58:34 -0800 | [diff] [blame^] | 8 | #ifndef SE_PRIVATE_H |
| 9 | #define SE_PRIVATE_H |
| Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 10 | |
| 11 | #include <lib/utils_def.h> |
| 12 | |
| 13 | /* SE0_INT_ENABLE_0 */ |
| 14 | #define SE0_INT_ENABLE U(0x88) |
| 15 | #define SE0_DISABLE_ALL_INT U(0x0) |
| 16 | |
| 17 | /* SE0_INT_STATUS_0 */ |
| 18 | #define SE0_INT_STATUS U(0x8C) |
| 19 | #define SE0_CLEAR_ALL_INT_STATUS U(0x3F) |
| 20 | |
| 21 | /* SE0_SHA_INT_STATUS_0 */ |
| 22 | #define SHA_INT_STATUS U(0x184) |
| 23 | #define SHA_SE_OP_DONE (U(1) << 4) |
| 24 | |
| 25 | /* SE0_SHA_ERR_STATUS_0 */ |
| 26 | #define SHA_ERR_STATUS U(0x18C) |
| 27 | |
| 28 | /* SE0_AES0_INT_STATUS_0 */ |
| 29 | #define AES0_INT_STATUS U(0x2F0) |
| 30 | #define AES0_SE_OP_DONE (U(1) << 4) |
| 31 | |
| 32 | /* SE0_AES0_ERR_STATUS_0 */ |
| 33 | #define AES0_ERR_STATUS U(0x2F8) |
| 34 | |
| 35 | /* SE0_AES1_INT_STATUS_0 */ |
| 36 | #define AES1_INT_STATUS U(0x4F0) |
| 37 | |
| 38 | /* SE0_AES1_ERR_STATUS_0 */ |
| 39 | #define AES1_ERR_STATUS U(0x4F8) |
| 40 | |
| 41 | /* SE0_RSA_INT_STATUS_0 */ |
| 42 | #define RSA_INT_STATUS U(0x758) |
| 43 | |
| 44 | /* SE0_RSA_ERR_STATUS_0 */ |
| 45 | #define RSA_ERR_STATUS U(0x760) |
| 46 | |
| 47 | /* SE0_AES0_OPERATION_0 */ |
| 48 | #define AES0_OPERATION U(0x238) |
| 49 | #define OP_MASK_BITS U(0x7) |
| 50 | #define SE_OP_CTX_SAVE U(0x3) |
| 51 | |
| 52 | /* SE0_AES0_CTX_SAVE_CONFIG_0 */ |
| 53 | #define CTX_SAVE_CONFIG U(0x2D4) |
| 54 | |
| 55 | /* SE0_AES0_CTX_SAVE_AUTO_STATUS_0 */ |
| 56 | #define CTX_SAVE_AUTO_STATUS U(0x300) |
| 57 | #define CTX_SAVE_AUTO_SE_READY U(0xFF) |
| 58 | #define CTX_SAVE_AUTO_SE_BUSY (U(0x1) << 31) |
| 59 | |
| 60 | /* SE0_AES0_CTX_SAVE_AUTO_CTRL_0 */ |
| 61 | #define CTX_SAVE_AUTO_CTRL U(0x304) |
| 62 | #define SE_CTX_SAVE_AUTO_EN (U(0x1) << 0) |
| 63 | #define SE_CTX_SAVE_AUTO_LOCK_EN (U(0x1) << 1) |
| 64 | |
| 65 | /* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_0 */ |
| 66 | #define CTX_SAVE_AUTO_START_ADDR U(0x308) |
| 67 | |
| 68 | /* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_HI_0 */ |
| 69 | #define CTX_SAVE_AUTO_START_ADDR_HI U(0x30C) |
| 70 | |
| 71 | /******************************************************************************* |
| 72 | * Inline functions definition |
| 73 | ******************************************************************************/ |
| 74 | |
| 75 | static inline uint32_t tegra_se_read_32(uint32_t offset) |
| 76 | { |
| 77 | return mmio_read_32(TEGRA_SE0_BASE + offset); |
| 78 | } |
| 79 | |
| 80 | static inline void tegra_se_write_32(uint32_t offset, uint32_t val) |
| 81 | { |
| 82 | mmio_write_32(TEGRA_SE0_BASE + offset, val); |
| 83 | } |
| 84 | |
| Varun Wadekar | 5528325 | 2020-01-09 08:58:34 -0800 | [diff] [blame^] | 85 | #endif /* SE_PRIVATE_H */ |