Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 1 | Build Options |
| 2 | ============= |
| 3 | |
| 4 | The TF-A build system supports the following build options. Unless mentioned |
| 5 | otherwise, these options are expected to be specified at the build command |
| 6 | line and are not to be modified in any component makefiles. Note that the |
| 7 | build system doesn't track dependency for build options. Therefore, if any of |
| 8 | the build options are changed from a previous build, a clean build must be |
| 9 | performed. |
| 10 | |
| 11 | .. _build_options_common: |
| 12 | |
| 13 | Common build options |
| 14 | -------------------- |
| 15 | |
| 16 | - ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the |
| 17 | compiler should use. Valid values are T32 and A32. It defaults to T32 due to |
| 18 | code having a smaller resulting size. |
| 19 | |
| 20 | - ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as |
| 21 | as the BL32 image when ``ARCH=aarch32``. The value should be the path to the |
| 22 | directory containing the SP source, relative to the ``bl32/``; the directory |
| 23 | is expected to contain a makefile called ``<aarch32_sp-value>.mk``. |
| 24 | |
| 25 | - ``ARCH`` : Choose the target build architecture for TF-A. It can take either |
| 26 | ``aarch64`` or ``aarch32`` as values. By default, it is defined to |
| 27 | ``aarch64``. |
| 28 | |
Alexei Fedorov | 132e665 | 2020-12-07 16:38:53 +0000 | [diff] [blame] | 29 | - ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies |
| 30 | one or more feature modifiers. This option has the form ``[no]feature+...`` |
| 31 | and defaults to ``none``. It translates into compiler option |
| 32 | ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the |
| 33 | list of supported feature modifiers. |
| 34 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 35 | - ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when |
| 36 | compiling TF-A. Its value must be numeric, and defaults to 8 . See also, |
| 37 | *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in |
| 38 | :ref:`Firmware Design`. |
| 39 | |
| 40 | - ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when |
| 41 | compiling TF-A. Its value must be a numeric, and defaults to 0. See also, |
| 42 | *Armv8 Architecture Extensions* in :ref:`Firmware Design`. |
| 43 | |
| 44 | - ``BL2``: This is an optional build option which specifies the path to BL2 |
| 45 | image for the ``fip`` target. In this case, the BL2 in the TF-A will not be |
| 46 | built. |
| 47 | |
| 48 | - ``BL2U``: This is an optional build option which specifies the path to |
| 49 | BL2U image. In this case, the BL2U in TF-A will not be built. |
| 50 | |
| 51 | - ``BL2_AT_EL3``: This is an optional build option that enables the use of |
| 52 | BL2 at EL3 execution level. |
| 53 | |
| 54 | - ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place |
| 55 | (XIP) memory, like BL1. In these use-cases, it is necessary to initialize |
| 56 | the RW sections in RAM, while leaving the RO sections in place. This option |
| 57 | enable this use-case. For now, this option is only supported when BL2_AT_EL3 |
| 58 | is set to '1'. |
| 59 | |
| 60 | - ``BL31``: This is an optional build option which specifies the path to |
| 61 | BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not |
| 62 | be built. |
| 63 | |
| 64 | - ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 65 | file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, |
| 66 | this file name will be used to save the key. |
| 67 | |
| 68 | - ``BL32``: This is an optional build option which specifies the path to |
| 69 | BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not |
| 70 | be built. |
| 71 | |
| 72 | - ``BL32_EXTRA1``: This is an optional build option which specifies the path to |
| 73 | Trusted OS Extra1 image for the ``fip`` target. |
| 74 | |
| 75 | - ``BL32_EXTRA2``: This is an optional build option which specifies the path to |
| 76 | Trusted OS Extra2 image for the ``fip`` target. |
| 77 | |
| 78 | - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 79 | file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, |
| 80 | this file name will be used to save the key. |
| 81 | |
| 82 | - ``BL33``: Path to BL33 image in the host file system. This is mandatory for |
| 83 | ``fip`` target in case TF-A BL2 is used. |
| 84 | |
| 85 | - ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 86 | file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, |
| 87 | this file name will be used to save the key. |
| 88 | |
| 89 | - ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication |
| 90 | and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. |
| 91 | If enabled, it is needed to use a compiler that supports the option |
| 92 | ``-mbranch-protection``. Selects the branch protection features to use: |
| 93 | - 0: Default value turns off all types of branch protection |
| 94 | - 1: Enables all types of branch protection features |
| 95 | - 2: Return address signing to its standard level |
| 96 | - 3: Extend the signing to include leaf functions |
Alexei Fedorov | e039e48 | 2020-06-19 14:33:49 +0100 | [diff] [blame] | 97 | - 4: Turn on branch target identification mechanism |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 98 | |
| 99 | The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options |
| 100 | and resulting PAuth/BTI features. |
| 101 | |
| 102 | +-------+--------------+-------+-----+ |
| 103 | | Value | GCC option | PAuth | BTI | |
| 104 | +=======+==============+=======+=====+ |
| 105 | | 0 | none | N | N | |
| 106 | +-------+--------------+-------+-----+ |
| 107 | | 1 | standard | Y | Y | |
| 108 | +-------+--------------+-------+-----+ |
| 109 | | 2 | pac-ret | Y | N | |
| 110 | +-------+--------------+-------+-----+ |
| 111 | | 3 | pac-ret+leaf | Y | N | |
| 112 | +-------+--------------+-------+-----+ |
Alexei Fedorov | e039e48 | 2020-06-19 14:33:49 +0100 | [diff] [blame] | 113 | | 4 | bti | N | Y | |
| 114 | +-------+--------------+-------+-----+ |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 115 | |
| 116 | This option defaults to 0 and this is an experimental feature. |
| 117 | Note that Pointer Authentication is enabled for Non-secure world |
| 118 | irrespective of the value of this option if the CPU supports it. |
| 119 | |
| 120 | - ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the |
| 121 | compilation of each build. It must be set to a C string (including quotes |
| 122 | where applicable). Defaults to a string that contains the time and date of |
| 123 | the compilation. |
| 124 | |
| 125 | - ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A |
| 126 | build to be uniquely identified. Defaults to the current git commit id. |
| 127 | |
Grant Likely | 388248a | 2020-07-30 08:50:10 +0100 | [diff] [blame] | 128 | - ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` |
| 129 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 130 | - ``CFLAGS``: Extra user options appended on the compiler's command line in |
| 131 | addition to the options set by the build system. |
| 132 | |
| 133 | - ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may |
| 134 | release several CPUs out of reset. It can take either 0 (several CPUs may be |
| 135 | brought up) or 1 (only one CPU will ever be brought up during cold reset). |
| 136 | Default is 0. If the platform always brings up a single CPU, there is no |
| 137 | need to distinguish between primary and secondary CPUs and the boot path can |
| 138 | be optimised. The ``plat_is_my_cpu_primary()`` and |
| 139 | ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need |
| 140 | to be implemented in this case. |
| 141 | |
Sandrine Bailleux | d4c1d44 | 2020-01-15 10:23:25 +0100 | [diff] [blame] | 142 | - ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. |
| 143 | Defaults to ``tbbr``. |
| 144 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 145 | - ``CRASH_REPORTING``: A non-zero value enables a console dump of processor |
| 146 | register state when an unexpected exception occurs during execution of |
| 147 | BL31. This option defaults to the value of ``DEBUG`` - i.e. by default |
| 148 | this is only enabled for a debug build of the firmware. |
| 149 | |
| 150 | - ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the |
| 151 | certificate generation tool to create new keys in case no valid keys are |
| 152 | present or specified. Allowed options are '0' or '1'. Default is '1'. |
| 153 | |
| 154 | - ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause |
| 155 | the AArch32 system registers to be included when saving and restoring the |
| 156 | CPU context. The option must be set to 0 for AArch64-only platforms (that |
| 157 | is on hardware that does not implement AArch32, or at least not at EL1 and |
| 158 | higher ELs). Default value is 1. |
| 159 | |
Olivier Deprez | 7efa3f1 | 2020-03-26 16:09:21 +0100 | [diff] [blame] | 160 | - ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore |
| 161 | operations when entering/exiting an EL2 execution context. This is of primary |
| 162 | interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). |
| 163 | This option must be equal to 1 (enabled) when ``SPD=spmd`` and |
| 164 | ``SPMD_SPM_AT_SEL2`` is set. |
| 165 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 166 | - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP |
| 167 | registers to be included when saving and restoring the CPU context. Default |
| 168 | is 0. |
| 169 | |
Arunachalam Ganapathy | dd3ec7e | 2020-05-28 11:57:09 +0100 | [diff] [blame] | 170 | - ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the |
| 171 | Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 |
| 172 | execution context. Default value is 0. |
| 173 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 174 | - ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables |
| 175 | Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth |
| 176 | registers to be included when saving and restoring the CPU context as |
| 177 | part of world switch. Default value is 0 and this is an experimental feature. |
| 178 | Note that Pointer Authentication is enabled for Non-secure world irrespective |
| 179 | of the value of this flag if the CPU supports it. |
| 180 | |
| 181 | - ``DEBUG``: Chooses between a debug and release build. It can take either 0 |
| 182 | (release) or 1 (debug) as values. 0 is the default. |
| 183 | |
Sumit Garg | 392e4df | 2019-11-15 10:43:00 +0530 | [diff] [blame] | 184 | - ``DECRYPTION_SUPPORT``: This build flag enables the user to select the |
| 185 | authenticated decryption algorithm to be used to decrypt firmware/s during |
| 186 | boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of |
| 187 | this flag is ``none`` to disable firmware decryption which is an optional |
| 188 | feature as per TBBR. Also, it is an experimental feature. |
| 189 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 190 | - ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation |
| 191 | of the binary image. If set to 1, then only the ELF image is built. |
| 192 | 0 is the default. |
| 193 | |
| 194 | - ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted |
| 195 | Board Boot authentication at runtime. This option is meant to be enabled only |
| 196 | for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this |
| 197 | flag has to be enabled. 0 is the default. |
| 198 | |
| 199 | - ``E``: Boolean option to make warnings into errors. Default is 1. |
| 200 | |
| 201 | - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of |
| 202 | the normal boot flow. It must specify the entry point address of the EL3 |
| 203 | payload. Please refer to the "Booting an EL3 payload" section for more |
| 204 | details. |
| 205 | |
| 206 | - ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. |
| 207 | This is an optional architectural feature available on v8.4 onwards. Some |
| 208 | v8.2 implementations also implement an AMU and this option can be used to |
| 209 | enable this feature on those systems as well. Default is 0. |
| 210 | |
| 211 | - ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` |
| 212 | are compiled out. For debug builds, this option defaults to 1, and calls to |
| 213 | ``assert()`` are left in place. For release builds, this option defaults to 0 |
| 214 | and calls to ``assert()`` function are compiled out. This option can be set |
| 215 | independently of ``DEBUG``. It can also be used to hide any auxiliary code |
| 216 | that is only required for the assertion and does not fit in the assertion |
| 217 | itself. |
| 218 | |
Alexei Fedorov | b8f26e9 | 2020-02-06 17:11:03 +0000 | [diff] [blame] | 219 | - ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 220 | dumps or not. It is supported in both AArch64 and AArch32. However, in |
| 221 | AArch32 the format of the frame records are not defined in the AAPCS and they |
| 222 | are defined by the implementation. This implementation of backtrace only |
| 223 | supports the format used by GCC when T32 interworking is disabled. For this |
| 224 | reason enabling this option in AArch32 will force the compiler to only |
| 225 | generate A32 code. This option is enabled by default only in AArch64 debug |
| 226 | builds, but this behaviour can be overridden in each platform's Makefile or |
| 227 | in the build command line. |
| 228 | |
Sandrine Bailleux | 1142730 | 2019-12-17 09:38:08 +0100 | [diff] [blame] | 229 | - ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) |
zelalem-aweke | d5f4527 | 2019-11-12 16:20:17 -0600 | [diff] [blame] | 230 | support in GCC for TF-A. This option is currently only supported for |
| 231 | AArch64. Default is 0. |
| 232 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 233 | - ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM |
| 234 | feature. MPAM is an optional Armv8.4 extension that enables various memory |
| 235 | system components and resources to define partitions; software running at |
| 236 | various ELs can assign themselves to desired partition to control their |
| 237 | performance aspects. |
| 238 | |
| 239 | When this option is set to ``1``, EL3 allows lower ELs to access their own |
| 240 | MPAM registers without trapping into EL3. This option doesn't make use of |
| 241 | partitioning in EL3, however. Platform initialisation code should configure |
| 242 | and use partitions in EL3 as required. This option defaults to ``0``. |
| 243 | |
| 244 | - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) |
| 245 | support within generic code in TF-A. This option is currently only supported |
Masahiro Yamada | de634f8 | 2020-01-17 13:45:14 +0900 | [diff] [blame] | 246 | in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 247 | |
| 248 | - ``ENABLE_PMF``: Boolean option to enable support for optional Performance |
| 249 | Measurement Framework(PMF). Default is 0. |
| 250 | |
| 251 | - ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI |
| 252 | functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. |
| 253 | In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must |
| 254 | be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in |
| 255 | software. |
| 256 | |
| 257 | - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime |
| 258 | instrumentation which injects timestamp collection points into TF-A to |
| 259 | allow runtime performance to be measured. Currently, only PSCI is |
| 260 | instrumented. Enabling this option enables the ``ENABLE_PMF`` build option |
| 261 | as well. Default is 0. |
| 262 | |
| 263 | - ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling |
| 264 | extensions. This is an optional architectural feature for AArch64. |
| 265 | The default is 1 but is automatically disabled when the target architecture |
| 266 | is AArch32. |
| 267 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 268 | - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension |
| 269 | (SVE) for the Non-secure world only. SVE is an optional architectural feature |
| 270 | for AArch64. Note that when SVE is enabled for the Non-secure world, access |
| 271 | to SIMD and floating-point functionality from the Secure world is disabled. |
| 272 | This is to avoid corruption of the Non-secure world data in the Z-registers |
| 273 | which are aliased by the SIMD and FP registers. The build option is not |
| 274 | compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an |
| 275 | assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to |
| 276 | 1. The default is 1 but is automatically disabled when the target |
| 277 | architecture is AArch32. |
| 278 | |
| 279 | - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection |
| 280 | checks in GCC. Allowed values are "all", "strong", "default" and "none". The |
| 281 | default value is set to "none". "strong" is the recommended stack protection |
| 282 | level if this feature is desired. "none" disables the stack protection. For |
| 283 | all values other than "none", the ``plat_get_stack_protector_canary()`` |
| 284 | platform hook needs to be implemented. The value is passed as the last |
| 285 | component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. |
| 286 | |
Sumit Garg | c0c369c | 2019-11-15 18:47:53 +0530 | [diff] [blame] | 287 | - ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This |
| 288 | flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as |
| 289 | experimental. |
| 290 | |
| 291 | - ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. |
| 292 | This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as |
| 293 | experimental. |
| 294 | |
| 295 | - ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could |
| 296 | either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends |
| 297 | on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental. |
| 298 | |
| 299 | - ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector |
| 300 | (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` |
| 301 | build flag which is marked as experimental. |
| 302 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 303 | - ``ERROR_DEPRECATED``: This option decides whether to treat the usage of |
| 304 | deprecated platform APIs, helper functions or drivers within Trusted |
| 305 | Firmware as error. It can take the value 1 (flag the use of deprecated |
| 306 | APIs as error) or 0. The default is 0. |
| 307 | |
| 308 | - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions |
| 309 | targeted at EL3. When set ``0`` (default), no exceptions are expected or |
| 310 | handled at EL3, and a panic will result. This is supported only for AArch64 |
| 311 | builds. |
| 312 | |
Javier Almansa Sobrino | 0d1f6b1 | 2020-09-18 16:47:07 +0100 | [diff] [blame] | 313 | - ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when |
| 314 | ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. |
| 315 | Default value is 40 (LOG_LEVEL_INFO). |
| 316 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 317 | - ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault |
| 318 | injection from lower ELs, and this build option enables lower ELs to use |
| 319 | Error Records accessed via System Registers to inject faults. This is |
| 320 | applicable only to AArch64 builds. |
| 321 | |
| 322 | This feature is intended for testing purposes only, and is advisable to keep |
| 323 | disabled for production images. |
| 324 | |
| 325 | - ``FIP_NAME``: This is an optional build option which specifies the FIP |
| 326 | filename for the ``fip`` target. Default is ``fip.bin``. |
| 327 | |
| 328 | - ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU |
| 329 | FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. |
| 330 | |
Sumit Garg | c0c369c | 2019-11-15 18:47:53 +0530 | [diff] [blame] | 331 | - ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: |
| 332 | |
| 333 | :: |
| 334 | |
| 335 | 0: Encryption is done with Secret Symmetric Key (SSK) which is common |
| 336 | for a class of devices. |
| 337 | 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is |
| 338 | unique per device. |
| 339 | |
| 340 | This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as |
| 341 | experimental. |
| 342 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 343 | - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` |
| 344 | tool to create certificates as per the Chain of Trust described in |
| 345 | :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to |
| 346 | include the certificates in the FIP and FWU_FIP. Default value is '0'. |
| 347 | |
| 348 | Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support |
| 349 | for the Trusted Board Boot feature in the BL1 and BL2 images, to generate |
| 350 | the corresponding certificates, and to include those certificates in the |
| 351 | FIP and FWU_FIP. |
| 352 | |
| 353 | Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 |
| 354 | images will not include support for Trusted Board Boot. The FIP will still |
| 355 | include the corresponding certificates. This FIP can be used to verify the |
| 356 | Chain of Trust on the host machine through other mechanisms. |
| 357 | |
| 358 | Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 |
| 359 | images will include support for Trusted Board Boot, but the FIP and FWU_FIP |
| 360 | will not include the corresponding certificates, causing a boot failure. |
| 361 | |
| 362 | - ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have |
| 363 | inherent support for specific EL3 type interrupts. Setting this build option |
| 364 | to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both |
Madhukar Pappireddy | 86350ae | 2020-07-29 09:37:25 -0500 | [diff] [blame] | 365 | by :ref:`platform abstraction layer<platform Interrupt Controller API>` and |
| 366 | :ref:`Interrupt Management Framework<Interrupt Management Framework>`. |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 367 | This allows GICv2 platforms to enable features requiring EL3 interrupt type. |
| 368 | This also means that all GICv2 Group 0 interrupts are delivered to EL3, and |
| 369 | the Secure Payload interrupts needs to be synchronously handed over to Secure |
| 370 | EL1 for handling. The default value of this option is ``0``, which means the |
| 371 | Group 0 interrupts are assumed to be handled by Secure EL1. |
| 372 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 373 | - ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError |
| 374 | Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to |
| 375 | ``0`` (default), these exceptions will be trapped in the current exception |
| 376 | level (or in EL1 if the current exception level is EL0). |
| 377 | |
| 378 | - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific |
| 379 | software operations are required for CPUs to enter and exit coherency. |
| 380 | However, newer systems exist where CPUs' entry to and exit from coherency |
| 381 | is managed in hardware. Such systems require software to only initiate these |
| 382 | operations, and the rest is managed in hardware, minimizing active software |
| 383 | management. In such systems, this boolean option enables TF-A to carry out |
| 384 | build and run-time optimizations during boot and power management operations. |
| 385 | This option defaults to 0 and if it is enabled, then it implies |
| 386 | ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. |
| 387 | |
| 388 | If this flag is disabled while the platform which TF-A is compiled for |
| 389 | includes cores that manage coherency in hardware, then a compilation error is |
| 390 | generated. This is based on the fact that a system cannot have, at the same |
| 391 | time, cores that manage coherency in hardware and cores that don't. In other |
| 392 | words, a platform cannot have, at the same time, cores that require |
| 393 | ``HW_ASSISTED_COHERENCY=1`` and cores that require |
| 394 | ``HW_ASSISTED_COHERENCY=0``. |
| 395 | |
| 396 | Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of |
| 397 | translation library (xlat tables v2) must be used; version 1 of translation |
| 398 | library is not supported. |
| 399 | |
Louis Mayencourt | c1c2bf7 | 2020-02-13 08:21:34 +0000 | [diff] [blame] | 400 | - ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the |
| 401 | bottom, higher addresses at the top. This buid flag can be set to '1' to |
| 402 | invert this behavior. Lower addresses will be printed at the top and higher |
| 403 | addresses at the bottom. |
| 404 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 405 | - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 |
| 406 | runtime software in AArch32 mode, which is required to run AArch32 on Juno. |
| 407 | By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in |
| 408 | AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable |
| 409 | images. |
| 410 | |
| 411 | - ``KEY_ALG``: This build flag enables the user to select the algorithm to be |
| 412 | used for generating the PKCS keys and subsequent signing of the certificate. |
| 413 | It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option |
| 414 | ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR |
| 415 | compliant and is retained only for compatibility. The default value of this |
| 416 | flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. |
| 417 | |
Gilad Ben-Yossef | a6e5342 | 2019-09-15 13:29:29 +0300 | [diff] [blame] | 418 | - ``KEY_SIZE``: This build flag enables the user to select the key size for |
| 419 | the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` |
| 420 | depend on the chosen algorithm and the cryptographic module. |
| 421 | |
| 422 | +-----------+------------------------------------+ |
| 423 | | KEY_ALG | Possible key sizes | |
| 424 | +===========+====================================+ |
| 425 | | rsa | 1024 , 2048 (default), 3072, 4096* | |
| 426 | +-----------+------------------------------------+ |
| 427 | | ecdsa | unavailable | |
| 428 | +-----------+------------------------------------+ |
| 429 | |
| 430 | * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. |
| 431 | Only 3072 bits size is available with CryptoCell 712 SBROM release 2. |
| 432 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 433 | - ``HASH_ALG``: This build flag enables the user to select the secure hash |
| 434 | algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. |
| 435 | The default value of this flag is ``sha256``. |
| 436 | |
| 437 | - ``LDFLAGS``: Extra user options appended to the linkers' command line in |
| 438 | addition to the one set by the build system. |
| 439 | |
| 440 | - ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log |
| 441 | output compiled into the build. This should be one of the following: |
| 442 | |
| 443 | :: |
| 444 | |
| 445 | 0 (LOG_LEVEL_NONE) |
| 446 | 10 (LOG_LEVEL_ERROR) |
| 447 | 20 (LOG_LEVEL_NOTICE) |
| 448 | 30 (LOG_LEVEL_WARNING) |
| 449 | 40 (LOG_LEVEL_INFO) |
| 450 | 50 (LOG_LEVEL_VERBOSE) |
| 451 | |
| 452 | All log output up to and including the selected log level is compiled into |
| 453 | the build. The default value is 40 in debug builds and 20 in release builds. |
| 454 | |
Alexei Fedorov | 913cb7e | 2020-01-23 14:27:38 +0000 | [diff] [blame] | 455 | - ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot |
| 456 | feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set. |
| 457 | This option defaults to 0 and is an experimental feature in the stage of |
| 458 | development. |
| 459 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 460 | - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It |
| 461 | specifies the file that contains the Non-Trusted World private key in PEM |
| 462 | format. If ``SAVE_KEYS=1``, this file name will be used to save the key. |
| 463 | |
| 464 | - ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is |
| 465 | optional. It is only needed if the platform makefile specifies that it |
| 466 | is required in order to build the ``fwu_fip`` target. |
| 467 | |
| 468 | - ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register |
| 469 | contents upon world switch. It can take either 0 (don't save and restore) or |
| 470 | 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it |
| 471 | wants the timer registers to be saved and restored. |
| 472 | |
| 473 | - ``OVERRIDE_LIBC``: This option allows platforms to override the default libc |
| 474 | for the BL image. It can be either 0 (include) or 1 (remove). The default |
| 475 | value is 0. |
| 476 | |
| 477 | - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that |
| 478 | the underlying hardware is not a full PL011 UART but a minimally compliant |
| 479 | generic UART, which is a subset of the PL011. The driver will not access |
| 480 | any register that is not part of the SBSA generic UART specification. |
| 481 | Default value is 0 (a full PL011 compliant UART is present). |
| 482 | |
| 483 | - ``PLAT``: Choose a platform to build TF-A for. The chosen platform name |
| 484 | must be subdirectory of any depth under ``plat/``, and must contain a |
| 485 | platform makefile named ``platform.mk``. For example, to build TF-A for the |
| 486 | Arm Juno board, select PLAT=juno. |
| 487 | |
| 488 | - ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image |
| 489 | instead of the normal boot flow. When defined, it must specify the entry |
| 490 | point address for the preloaded BL33 image. This option is incompatible with |
| 491 | ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority |
| 492 | over ``PRELOADED_BL33_BASE``. |
| 493 | |
| 494 | - ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset |
| 495 | vector address can be programmed or is fixed on the platform. It can take |
| 496 | either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a |
| 497 | programmable reset address, it is expected that a CPU will start executing |
| 498 | code directly at the right address, both on a cold and warm reset. In this |
| 499 | case, there is no need to identify the entrypoint on boot and the boot path |
| 500 | can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface |
| 501 | does not need to be implemented in this case. |
| 502 | |
| 503 | - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats |
| 504 | possible for the PSCI power-state parameter: original and extended State-ID |
| 505 | formats. This flag if set to 1, configures the generic PSCI layer to use the |
| 506 | extended format. The default value of this flag is 0, which means by default |
| 507 | the original power-state format is used by the PSCI implementation. This flag |
| 508 | should be specified by the platform makefile and it governs the return value |
| 509 | of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is |
| 510 | enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be |
| 511 | set to 1 as well. |
| 512 | |
| 513 | - ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features |
| 514 | are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 |
| 515 | or later CPUs. |
| 516 | |
| 517 | When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be |
| 518 | set to ``1``. |
| 519 | |
| 520 | This option is disabled by default. |
| 521 | |
| 522 | - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead |
| 523 | of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 |
| 524 | entrypoint) or 1 (CPU reset to BL31 entrypoint). |
| 525 | The default value is 0. |
| 526 | |
| 527 | - ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided |
| 528 | in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector |
| 529 | instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 |
| 530 | entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. |
| 531 | |
| 532 | - ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 533 | file that contains the ROT private key in PEM format and enforces public key |
| 534 | hash generation. If ``SAVE_KEYS=1``, this |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 535 | file name will be used to save the key. |
| 536 | |
| 537 | - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the |
| 538 | certificate generation tool to save the keys used to establish the Chain of |
| 539 | Trust. Allowed options are '0' or '1'. Default is '0' (do not save). |
| 540 | |
| 541 | - ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. |
| 542 | If a SCP_BL2 image is present then this option must be passed for the ``fip`` |
| 543 | target. |
| 544 | |
| 545 | - ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 546 | file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, |
| 547 | this file name will be used to save the key. |
| 548 | |
| 549 | - ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is |
| 550 | optional. It is only needed if the platform makefile specifies that it |
| 551 | is required in order to build the ``fwu_fip`` target. |
| 552 | |
| 553 | - ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software |
| 554 | Delegated Exception Interface to BL31 image. This defaults to ``0``. |
| 555 | |
| 556 | When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be |
| 557 | set to ``1``. |
| 558 | |
| 559 | - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be |
| 560 | isolated on separate memory pages. This is a trade-off between security and |
| 561 | memory usage. See "Isolating code and read-only data on separate memory |
Olivier Deprez | 7efa3f1 | 2020-03-26 16:09:21 +0100 | [diff] [blame] | 562 | pages" section in :ref:`Firmware Design`. This flag is disabled by default |
| 563 | and affects all BL images. |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 564 | |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 565 | - ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS |
| 566 | sections of BL31 (.bss, stacks, page tables, and coherent memory) to be |
| 567 | allocated in RAM discontiguous from the loaded firmware image. When set, the |
| 568 | platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and |
| 569 | ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS |
| 570 | sections are placed in RAM immediately following the loaded firmware image. |
| 571 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 572 | - ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. |
| 573 | This build option is only valid if ``ARCH=aarch64``. The value should be |
| 574 | the path to the directory containing the SPD source, relative to |
| 575 | ``services/spd/``; the directory is expected to contain a makefile called |
Olivier Deprez | 7efa3f1 | 2020-03-26 16:09:21 +0100 | [diff] [blame] | 576 | ``<spd-value>.mk``. The SPM Dispatcher standard service is located in |
| 577 | services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher |
| 578 | cannot be enabled when the ``SPM_MM`` option is enabled. |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 579 | |
| 580 | - ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can |
| 581 | take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops |
| 582 | execution in BL1 just before handing over to BL31. At this point, all |
| 583 | firmware images have been loaded in memory, and the MMU and caches are |
| 584 | turned off. Refer to the "Debugging options" section for more details. |
| 585 | |
Olivier Deprez | 7efa3f1 | 2020-03-26 16:09:21 +0100 | [diff] [blame] | 586 | - ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM |
| 587 | Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC |
| 588 | component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 |
| 589 | extension. This is the default when enabling the SPM Dispatcher. When |
| 590 | disabled (0) it indicates the SPMC component runs at the S-EL1 execution |
| 591 | state. This latter configuration supports pre-Armv8.4 platforms (aka not |
| 592 | implementing the Armv8.4-SecEL2 extension). |
| 593 | |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 594 | - ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure |
Olivier Deprez | 7efa3f1 | 2020-03-26 16:09:21 +0100 | [diff] [blame] | 595 | Partition Manager (SPM) implementation. The default value is ``0`` |
| 596 | (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is |
| 597 | enabled (``SPD=spmd``). |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 598 | |
Manish Pandey | 3f90ad7 | 2020-01-14 11:52:05 +0000 | [diff] [blame] | 599 | - ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the |
Olivier Deprez | 7efa3f1 | 2020-03-26 16:09:21 +0100 | [diff] [blame] | 600 | description of secure partitions. The build system will parse this file and |
| 601 | package all secure partition blobs into the FIP. This file is not |
| 602 | necessarily part of TF-A tree. Only available when ``SPD=spmd``. |
Manish Pandey | 3f90ad7 | 2020-01-14 11:52:05 +0000 | [diff] [blame] | 603 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 604 | - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles |
| 605 | secure interrupts (caught through the FIQ line). Platforms can enable |
| 606 | this directive if they need to handle such interruption. When enabled, |
| 607 | the FIQ are handled in monitor mode and non secure world is not allowed |
| 608 | to mask these events. Platforms that enable FIQ handling in SP_MIN shall |
| 609 | implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. |
| 610 | |
| 611 | - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board |
| 612 | Boot feature. When set to '1', BL1 and BL2 images include support to load |
| 613 | and verify the certificates and images in a FIP, and BL1 includes support |
| 614 | for the Firmware Update. The default value is '0'. Generation and inclusion |
| 615 | of certificates in the FIP and FWU_FIP depends upon the value of the |
| 616 | ``GENERATE_COT`` option. |
| 617 | |
| 618 | .. warning:: |
| 619 | This option depends on ``CREATE_KEYS`` to be enabled. If the keys |
| 620 | already exist in disk, they will be overwritten without further notice. |
| 621 | |
| 622 | - ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It |
| 623 | specifies the file that contains the Trusted World private key in PEM |
| 624 | format. If ``SAVE_KEYS=1``, this file name will be used to save the key. |
| 625 | |
| 626 | - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or |
| 627 | synchronous, (see "Initializing a BL32 Image" section in |
| 628 | :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using |
| 629 | synchronous method) or 1 (BL32 is initialized using asynchronous method). |
| 630 | Default is 0. |
| 631 | |
| 632 | - ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt |
| 633 | routing model which routes non-secure interrupts asynchronously from TSP |
| 634 | to EL3 causing immediate preemption of TSP. The EL3 is responsible |
| 635 | for saving and restoring the TSP context in this routing model. The |
| 636 | default routing model (when the value is 0) is to route non-secure |
| 637 | interrupts to TSP allowing it to save its context and hand over |
| 638 | synchronously to EL3 via an SMC. |
| 639 | |
| 640 | .. note:: |
| 641 | When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` |
| 642 | must also be set to ``1``. |
| 643 | |
| 644 | - ``USE_ARM_LINK``: This flag determines whether to enable support for ARM |
| 645 | linker. When the ``LINKER`` build variable points to the armlink linker, |
| 646 | this flag is enabled automatically. To enable support for armlink, platforms |
| 647 | will have to provide a scatter file for the BL image. Currently, Tegra |
| 648 | platforms use the armlink support to compile BL3-1 images. |
| 649 | |
| 650 | - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent |
| 651 | memory region in the BL memory map or not (see "Use of Coherent memory in |
| 652 | TF-A" section in :ref:`Firmware Design`). It can take the value 1 |
| 653 | (Coherent memory region is included) or 0 (Coherent memory region is |
| 654 | excluded). Default is 1. |
| 655 | |
Ambroise Vincent | 9660dc1 | 2019-07-12 13:47:03 +0100 | [diff] [blame] | 656 | - ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature |
| 657 | exposing a virtual filesystem interface through BL31 as a SiP SMC function. |
| 658 | Default is 0. |
| 659 | |
Louis Mayencourt | 6b232d9 | 2020-02-28 16:57:30 +0000 | [diff] [blame] | 660 | - ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the |
| 661 | firmware configuration framework. This will move the io_policies into a |
Louis Mayencourt | badcac8 | 2019-10-24 15:18:46 +0100 | [diff] [blame] | 662 | configuration device tree, instead of static structure in the code base. |
Louis Mayencourt | b25b8b6 | 2020-04-09 16:32:20 +0100 | [diff] [blame] | 663 | This is currently an experimental feature. |
Louis Mayencourt | badcac8 | 2019-10-24 15:18:46 +0100 | [diff] [blame] | 664 | |
Manish V Badarkhe | ad33989 | 2020-06-29 10:32:53 +0100 | [diff] [blame] | 665 | - ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors |
| 666 | at runtime using fconf. If this flag is enabled, COT descriptors are |
| 667 | statically captured in tb_fw_config file in the form of device tree nodes |
| 668 | and properties. Currently, COT descriptors used by BL2 are moved to the |
| 669 | device tree and COT descriptors used by BL1 are retained in the code |
| 670 | base statically. This is currently an experimental feature. |
| 671 | |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 672 | - ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in |
| 673 | runtime using firmware configuration framework. The platform specific SDEI |
| 674 | shared and private events configuration is retrieved from device tree rather |
| 675 | than static C structures at compile time. This is currently an experimental |
| 676 | feature and is only supported if SDEI_SUPPORT build flag is enabled. |
Louis Mayencourt | badcac8 | 2019-10-24 15:18:46 +0100 | [diff] [blame] | 677 | |
Madhukar Pappireddy | 02cc3ff | 2020-06-02 09:26:30 -0500 | [diff] [blame] | 678 | - ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 |
| 679 | and Group1 secure interrupts using the firmware configuration framework. The |
| 680 | platform specific secure interrupt property descriptor is retrieved from |
| 681 | device tree in runtime rather than depending on static C structure at compile |
| 682 | time. This is currently an experimental feature. |
| 683 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 684 | - ``USE_ROMLIB``: This flag determines whether library at ROM will be used. |
| 685 | This feature creates a library of functions to be placed in ROM and thus |
| 686 | reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default |
| 687 | is 0. |
| 688 | |
| 689 | - ``V``: Verbose build. If assigned anything other than 0, the build commands |
| 690 | are printed. Default is 0. |
| 691 | |
| 692 | - ``VERSION_STRING``: String used in the log output for each TF-A image. |
| 693 | Defaults to a string formed by concatenating the version number, build type |
| 694 | and build string. |
| 695 | |
| 696 | - ``W``: Warning level. Some compiler warning options of interest have been |
| 697 | regrouped and put in the root Makefile. This flag can take the values 0 to 3, |
| 698 | each level enabling more warning options. Default is 0. |
| 699 | |
| 700 | - ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on |
| 701 | the CPU after warm boot. This is applicable for platforms which do not |
| 702 | require interconnect programming to enable cache coherency (eg: single |
| 703 | cluster platforms). If this option is enabled, then warm boot path |
| 704 | enables D-caches immediately after enabling MMU. This option defaults to 0. |
| 705 | |
Manish V Badarkhe | 75c972a | 2020-03-22 05:06:38 +0000 | [diff] [blame] | 706 | - ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory |
| 707 | tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The |
| 708 | default value of this flag is ``no``. Note this option must be enabled only |
| 709 | for ARM architecture greater than Armv8.5-A. |
| 710 | |
Manish V Badarkhe | a59fa01 | 2020-07-31 08:38:49 +0100 | [diff] [blame] | 711 | - ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` |
| 712 | speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. |
| 713 | The default value of this flag is ``0``. |
| 714 | |
| 715 | ``AT`` speculative errata workaround disables stage1 page table walk for |
| 716 | lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point |
| 717 | produces either the correct result or failure without TLB allocation. |
Manish V Badarkhe | 2801ed4 | 2020-04-28 04:53:32 +0100 | [diff] [blame] | 718 | |
| 719 | This boolean option enables errata for all below CPUs. |
| 720 | |
Manish V Badarkhe | a59fa01 | 2020-07-31 08:38:49 +0100 | [diff] [blame] | 721 | +---------+--------------+-------------------------+ |
| 722 | | Errata | CPU | Workaround Define | |
| 723 | +=========+==============+=========================+ |
| 724 | | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | |
| 725 | +---------+--------------+-------------------------+ |
| 726 | | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | |
| 727 | +---------+--------------+-------------------------+ |
| 728 | | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | |
| 729 | +---------+--------------+-------------------------+ |
| 730 | | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | |
| 731 | +---------+--------------+-------------------------+ |
| 732 | | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | |
| 733 | +---------+--------------+-------------------------+ |
| 734 | |
| 735 | .. note:: |
| 736 | This option is enabled by build only if platform sets any of above defines |
| 737 | mentioned in ’Workaround Define' column in the table. |
| 738 | If this option is enabled for the EL3 software then EL2 software also must |
| 739 | implement this workaround due to the behaviour of the errata mentioned |
| 740 | in new SDEN document which will get published soon. |
Manish V Badarkhe | 2801ed4 | 2020-04-28 04:53:32 +0100 | [diff] [blame] | 741 | |
Varun Wadekar | 9223485 | 2020-06-12 10:11:28 -0700 | [diff] [blame] | 742 | - ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR |
| 743 | bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. |
| 744 | This flag is disabled by default. |
| 745 | |
Manish V Badarkhe | 3589b70 | 2020-07-29 10:58:44 +0100 | [diff] [blame] | 746 | - ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory |
| 747 | path on the host machine which is used to build certificate generation and |
| 748 | firmware encryption tool. |
| 749 | |
Madhukar Pappireddy | 7a554a1 | 2020-08-12 13:18:19 -0500 | [diff] [blame] | 750 | - ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for |
| 751 | functions that wait for an arbitrary time length (udelay and mdelay). The |
| 752 | default value is 0. |
| 753 | |
Alexei Fedorov | 84f1b5d | 2020-03-23 18:45:17 +0000 | [diff] [blame] | 754 | GICv3 driver options |
| 755 | -------------------- |
| 756 | |
| 757 | GICv3 driver files are included using directive: |
| 758 | |
| 759 | ``include drivers/arm/gic/v3/gicv3.mk`` |
| 760 | |
| 761 | The driver can be configured with the following options set in the platform |
| 762 | makefile: |
| 763 | |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 764 | - ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. |
| 765 | Enabling this option will add runtime detection support for the |
| 766 | GIC-600, so is safe to select even for a GIC500 implementation. |
| 767 | This option defaults to 0. |
Alexei Fedorov | 84f1b5d | 2020-03-23 18:45:17 +0000 | [diff] [blame] | 768 | |
| 769 | - ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip |
| 770 | functionality. This option defaults to 0 |
| 771 | |
| 772 | - ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation |
| 773 | of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` |
| 774 | functions. This is required for FVP platform which need to simulate GIC save |
| 775 | and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. |
| 776 | |
Alexei Fedorov | 1970593 | 2020-04-06 19:00:35 +0100 | [diff] [blame] | 777 | - ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. |
| 778 | This option defaults to 0. |
| 779 | |
Alexei Fedorov | a6e6ae0 | 2020-04-06 16:27:54 +0100 | [diff] [blame] | 780 | - ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended |
| 781 | PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. |
| 782 | |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 783 | Debugging options |
| 784 | ----------------- |
| 785 | |
| 786 | To compile a debug version and make the build more verbose use |
| 787 | |
| 788 | .. code:: shell |
| 789 | |
| 790 | make PLAT=<platform> DEBUG=1 V=1 all |
| 791 | |
| 792 | AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for |
| 793 | example DS-5) might not support this and may need an older version of DWARF |
| 794 | symbols to be emitted by GCC. This can be achieved by using the |
| 795 | ``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the |
| 796 | version to 2 is recommended for DS-5 versions older than 5.16. |
| 797 | |
| 798 | When debugging logic problems it might also be useful to disable all compiler |
| 799 | optimizations by using ``-O0``. |
| 800 | |
| 801 | .. warning:: |
| 802 | Using ``-O0`` could cause output images to be larger and base addresses |
| 803 | might need to be recalculated (see the **Memory layout on Arm development |
| 804 | platforms** section in the :ref:`Firmware Design`). |
| 805 | |
| 806 | Extra debug options can be passed to the build system by setting ``CFLAGS`` or |
| 807 | ``LDFLAGS``: |
| 808 | |
| 809 | .. code:: shell |
| 810 | |
| 811 | CFLAGS='-O0 -gdwarf-2' \ |
| 812 | make PLAT=<platform> DEBUG=1 V=1 all |
| 813 | |
| 814 | Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be |
| 815 | ignored as the linker is called directly. |
| 816 | |
| 817 | It is also possible to introduce an infinite loop to help in debugging the |
| 818 | post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the |
| 819 | ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` |
| 820 | section. In this case, the developer may take control of the target using a |
| 821 | debugger when indicated by the console output. When using DS-5, the following |
| 822 | commands can be used: |
| 823 | |
| 824 | :: |
| 825 | |
| 826 | # Stop target execution |
| 827 | interrupt |
| 828 | |
| 829 | # |
| 830 | # Prepare your debugging environment, e.g. set breakpoints |
| 831 | # |
| 832 | |
| 833 | # Jump over the debug loop |
| 834 | set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 |
| 835 | |
| 836 | # Resume execution |
| 837 | continue |
| 838 | |
| 839 | -------------- |
| 840 | |
Imre Kis | c83f720 | 2020-02-03 14:48:21 +0100 | [diff] [blame] | 841 | *Copyright (c) 2019-2020, Arm Limited. All rights reserved.* |