| developer | 550bf5e | 2016-07-11 16:05:23 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <cci.h> |
| 32 | #include <gic_v2.h> |
| 33 | #include <platform_def.h> |
| 34 | |
| 35 | .section .rodata.gic_reg_name, "aS" |
| 36 | gicc_regs: |
| 37 | .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" |
| 38 | gicd_pend_reg: |
| 39 | .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ |
| 40 | " Offset:\t\t\tvalue\n" |
| 41 | newline: |
| 42 | .asciz "\n" |
| 43 | spacer: |
| 44 | .asciz ":\t\t0x" |
| 45 | |
| 46 | /* --------------------------------------------- |
| 47 | * The below macro prints out relevant GIC |
| 48 | * registers whenever an unhandled exception is |
| 49 | * taken in BL3-1. |
| 50 | * Clobbers: x0 - x10, x16, x17, sp |
| 51 | * --------------------------------------------- |
| 52 | */ |
| 53 | .macro plat_crash_print_regs |
| 54 | mov_imm x16, BASE_GICD_BASE |
| 55 | mov_imm x17, BASE_GICC_BASE |
| 56 | /* Load the gicc reg list to x6 */ |
| 57 | adr x6, gicc_regs |
| 58 | /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ |
| 59 | ldr w8, [x17, #GICC_HPPIR] |
| 60 | ldr w9, [x17, #GICC_AHPPIR] |
| 61 | ldr w10, [x17, #GICC_CTLR] |
| 62 | /* Store to the crash buf and print to console */ |
| 63 | bl str_in_crash_buf_print |
| 64 | |
| 65 | /* Print the GICD_ISPENDR regs */ |
| 66 | add x7, x16, #GICD_ISPENDR |
| 67 | adr x4, gicd_pend_reg |
| 68 | bl asm_print_str |
| 69 | gicd_ispendr_loop: |
| 70 | sub x4, x7, x16 |
| 71 | cmp x4, #0x280 |
| 72 | b.eq exit_print_gic_regs |
| 73 | bl asm_print_hex |
| 74 | |
| 75 | adr x4, spacer |
| 76 | bl asm_print_str |
| 77 | |
| 78 | ldr x4, [x7], #8 |
| 79 | bl asm_print_hex |
| 80 | |
| 81 | adr x4, newline |
| 82 | bl asm_print_str |
| 83 | b gicd_ispendr_loop |
| 84 | exit_print_gic_regs: |
| 85 | .endm |
| 86 | |
| 87 | .section .rodata.cci_reg_name, "aS" |
| 88 | cci_iface_regs: |
| 89 | .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" |
| 90 | |
| 91 | /* ------------------------------------------------ |
| 92 | * The below macro prints out relevant interconnect |
| 93 | * registers whenever an unhandled exception is |
| 94 | * taken in BL3-1. |
| 95 | * Clobbers: x0 - x9, sp |
| 96 | * ------------------------------------------------ |
| 97 | */ |
| 98 | .macro plat_print_interconnect_regs |
| 99 | adr x6, cci_iface_regs |
| 100 | /* Store in x7 the base address of the first interface */ |
| 101 | mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ |
| 102 | PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX)) |
| 103 | ldr w8, [x7, #SNOOP_CTRL_REG] |
| 104 | /* Store in x7 the base address of the second interface */ |
| 105 | mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ |
| 106 | PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX)) |
| 107 | ldr w9, [x7, #SNOOP_CTRL_REG] |
| 108 | /* Store to the crash buf and print to console */ |
| 109 | bl str_in_crash_buf_print |
| 110 | .endm |