Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 550bf5ea93dcf20ac733e7f067b2ef9ddddf1b23 / . / plat / mediatek / mt6795 / aarch64 / plat_helpers.S
blob: eb0611afce01041533b7e56ca25e1d0851a7c96c [file] [log] [blame]
developer550bf5e2016-07-11 16:05:23 +0800[diff] [blame^]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arch.h>
31#include <asm_macros.S>
32#include <platform_def.h>
33
34 .globl plat_secondary_cold_boot_setup
35 .globl plat_report_exception
36 .globl platform_is_primary_cpu
37 .globl plat_crash_console_init
38 .globl plat_crash_console_putc
39 .globl platform_mem_init
40
41
42 .macro crash_ram_log
43 /*
44 * Check teearg->atf_log_buf_size.
45 * Exit if atf_log_buf_size equals 0
46 */
47 adr x2, ptr_atf_crash_flag
48 ldr x2, [x2]
49 /* exit if ptr_atf_crash_flag equals NULL */
50 cbz x2, exit_putc
51
52 /*
53 * set atf crash magic number
54 */
551:
56 adr x2, ptr_atf_crash_flag
57 ldr x2, [x2]
58 mov_imm x1, 0xdead1abf
59 /* p_atf_log_ctrl->atf_crash_flag = 0xdead1abf */
60 str w1, [x2]
61 /* can't use w3 return addr, w4, start of buffer addr */
62 ldr w2, [x2]
63 cmp w2, w1
64 b.ne 1b
65
66 /*
67 * get cpu id
68 */
69 mrs x1, mpidr_el1
70 /* refer to platform_get_core_pos */
71 and x2, x1, #MPIDR_CPU_MASK
72 and x1, x1, #MPIDR_CLUSTER_MASK
73 /* x1 = cpu id (cpu id = aff0 + aff1*4 ) */
74 add x1, x2, x1, LSR #6
75
76 adr x2, ptr_atf_except_write_pos_per_cpu
77 ldr x2, [x2]
78 /*
79 * plus (cpu_id * 8)-->
80 * &p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id]
81 * x2 = &p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id];
82 */
83 add x2, x2, x1, LSL # 3
84 /* log write */
85 /* w1 = p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id] */
86 ldr x1, [x2]
87 /* *x1 = w0-->
88 * *(p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id]) = c)
89 */
90 strb w0, [x1]
91 /* w1++ */
92 add x1, x1, #1
93 /* p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id] = w1 */
94 str x1, [x2]
95exit_putc:
96 .endm
97
98 /* -----------------------------------------------------
99 * void plat_secondary_cold_boot_setup (void);
100 *
101 * This function performs any platform specific actions
102 * needed for a secondary cpu after a cold reset e.g
103 * mark the cpu's presence, mechanism to place it in a
104 * holding pen etc.
105 * -----------------------------------------------------
106 */
107func plat_secondary_cold_boot_setup
108 /* Do not do cold boot for secondary CPU */
109cb_panic:
110 b cb_panic
111endfunc plat_secondary_cold_boot_setup
112
113func platform_is_primary_cpu
114 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
115 cmp x0, #PLAT_PRIMARY_CPU
116 cset x0, eq
117 ret
118endfunc platform_is_primary_cpu
119
120 /* ---------------------------------------------
121 * int plat_crash_console_init(void)
122 * Function to initialize the crash console
123 * without a C Runtime to print crash report.
124 * Clobber list : x0, x1, x2
125 * ---------------------------------------------
126 */
127func plat_crash_console_init
128 mov_imm x0, UART0_BASE
129 mov_imm x1, UART_CLOCK
130 mov_imm x2, UART_BAUDRATE
131 b console_init
132 ret
133endfunc plat_crash_console_init
134
135 /* ---------------------------------------------
136 * int plat_crash_console_putc(void)
137 * Function to print a character on the crash
138 * console without a C Runtime.
139 * Clobber list : x1, x2
140 * ---------------------------------------------
141 */
142func plat_crash_console_putc
143 mov_imm x1, UART0_BASE
144 b console_core_putc
145 ret
146endfunc plat_crash_console_putc
147
148 /* --------------------------------------------------------
149 * void platform_mem_init (void);
150 *
151 * Any memory init, relocation to be done before the
152 * platform boots. Called very early in the boot process.
153 * --------------------------------------------------------
154 */
155func platform_mem_init
156 ret
157endfunc platform_mem_init
158