Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <asm_macros.S> |
| 33 | #include <bl_common.h> |
| 34 | #include <cortex_a35.h> |
| 35 | #include <cpu_macros.S> |
| 36 | #include <plat_macros.S> |
| 37 | |
| 38 | /* --------------------------------------------- |
| 39 | * Disable L1 data cache and unified L2 cache |
| 40 | * --------------------------------------------- |
| 41 | */ |
| 42 | func cortex_a35_disable_dcache |
| 43 | mrs x1, sctlr_el3 |
| 44 | bic x1, x1, #SCTLR_C_BIT |
| 45 | msr sctlr_el3, x1 |
| 46 | isb |
| 47 | ret |
| 48 | endfunc cortex_a35_disable_dcache |
| 49 | |
| 50 | /* --------------------------------------------- |
| 51 | * Disable intra-cluster coherency |
| 52 | * --------------------------------------------- |
| 53 | */ |
| 54 | func cortex_a35_disable_smp |
| 55 | mrs x0, CORTEX_A35_CPUECTLR_EL1 |
| 56 | bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT |
| 57 | msr CORTEX_A35_CPUECTLR_EL1, x0 |
| 58 | isb |
| 59 | dsb sy |
| 60 | ret |
| 61 | endfunc cortex_a35_disable_smp |
| 62 | |
| 63 | /* ------------------------------------------------- |
| 64 | * The CPU Ops reset function for Cortex-A35. |
| 65 | * Clobbers: x0 |
| 66 | * ------------------------------------------------- |
| 67 | */ |
| 68 | func cortex_a35_reset_func |
| 69 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 70 | * Enable the SMP bit. |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 71 | * --------------------------------------------- |
| 72 | */ |
| 73 | mrs x0, CORTEX_A35_CPUECTLR_EL1 |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 74 | orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT |
| 75 | msr CORTEX_A35_CPUECTLR_EL1, x0 |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 76 | isb |
| 77 | ret |
| 78 | endfunc cortex_a35_reset_func |
| 79 | |
| 80 | func cortex_a35_core_pwr_dwn |
| 81 | mov x18, x30 |
| 82 | |
| 83 | /* --------------------------------------------- |
| 84 | * Turn off caches. |
| 85 | * --------------------------------------------- |
| 86 | */ |
| 87 | bl cortex_a35_disable_dcache |
| 88 | |
| 89 | /* --------------------------------------------- |
| 90 | * Flush L1 caches. |
| 91 | * --------------------------------------------- |
| 92 | */ |
| 93 | mov x0, #DCCISW |
| 94 | bl dcsw_op_level1 |
| 95 | |
| 96 | /* --------------------------------------------- |
| 97 | * Come out of intra cluster coherency |
| 98 | * --------------------------------------------- |
| 99 | */ |
| 100 | mov x30, x18 |
| 101 | b cortex_a35_disable_smp |
| 102 | endfunc cortex_a35_core_pwr_dwn |
| 103 | |
| 104 | func cortex_a35_cluster_pwr_dwn |
| 105 | mov x18, x30 |
| 106 | |
| 107 | /* --------------------------------------------- |
| 108 | * Turn off caches. |
| 109 | * --------------------------------------------- |
| 110 | */ |
| 111 | bl cortex_a35_disable_dcache |
| 112 | |
| 113 | /* --------------------------------------------- |
| 114 | * Flush L1 caches. |
| 115 | * --------------------------------------------- |
| 116 | */ |
| 117 | mov x0, #DCCISW |
| 118 | bl dcsw_op_level1 |
| 119 | |
| 120 | /* --------------------------------------------- |
| 121 | * Disable the optional ACP. |
| 122 | * --------------------------------------------- |
| 123 | */ |
| 124 | bl plat_disable_acp |
| 125 | |
| 126 | /* --------------------------------------------- |
| 127 | * Flush L2 caches. |
| 128 | * --------------------------------------------- |
| 129 | */ |
| 130 | mov x0, #DCCISW |
| 131 | bl dcsw_op_level2 |
| 132 | |
| 133 | /* --------------------------------------------- |
| 134 | * Come out of intra cluster coherency |
| 135 | * --------------------------------------------- |
| 136 | */ |
| 137 | mov x30, x18 |
| 138 | b cortex_a35_disable_smp |
| 139 | endfunc cortex_a35_cluster_pwr_dwn |
| 140 | |
| 141 | /* --------------------------------------------- |
| 142 | * This function provides cortex_a35 specific |
| 143 | * register information for crash reporting. |
| 144 | * It needs to return with x6 pointing to |
| 145 | * a list of register names in ascii and |
| 146 | * x8 - x15 having values of registers to be |
| 147 | * reported. |
| 148 | * --------------------------------------------- |
| 149 | */ |
| 150 | .section .rodata.cortex_a35_regs, "aS" |
| 151 | cortex_a35_regs: /* The ascii list of register names to be reported */ |
| 152 | .asciz "cpuectlr_el1", "" |
| 153 | |
| 154 | func cortex_a35_cpu_reg_dump |
| 155 | adr x6, cortex_a35_regs |
| 156 | mrs x8, CORTEX_A35_CPUECTLR_EL1 |
| 157 | ret |
| 158 | endfunc cortex_a35_cpu_reg_dump |
| 159 | |
| 160 | declare_cpu_ops cortex_a35, CORTEX_A35_MIDR |