blob: 94c4c5b38a1c4507459c8b569119174ed6deeb16 [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautierf9d40d52019-01-17 14:41:46 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Yann Gautier57e282b2019-01-07 11:17:24 +010017#ifndef __ASSEMBLY__
Yann Gautierb5d2ed42019-02-14 11:13:50 +010018#include <drivers/st/stm32mp1_clk.h>
19
Yann Gautier57e282b2019-01-07 11:17:24 +010020#include <boot_api.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010021#include <stm32mp_common.h>
22#include <stm32mp_dt.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010023#include <stm32mp_shres_helpers.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010024#include <stm32mp1_private.h>
25#endif
26
Yann Gautier4b0c72a2018-07-16 10:54:09 +020027/*******************************************************************************
28 * STM32MP1 memory map related constants
29 ******************************************************************************/
30
Yann Gautiera2e2a302019-02-14 11:13:39 +010031#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
32#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020033
34/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +010035#define STM32MP_DDR_BASE U(0xC0000000)
36#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautierb3386f72019-04-19 09:41:01 +020037#ifdef AARCH32_SP_OPTEE
38#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
39#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
40#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020041
42/* DDR power initializations */
43#ifndef __ASSEMBLY__
44enum ddr_type {
45 STM32MP_DDR3,
46 STM32MP_LPDDR2,
47};
48#endif
49
50/* Section used inside TF binaries */
Yann Gautiera2e2a302019-02-14 11:13:39 +010051#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020052/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +010053#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020054
Yann Gautiera2e2a302019-02-14 11:13:39 +010055#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
56 STM32MP_PARAM_LOAD_SIZE + \
57 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020058
Yann Gautiera2e2a302019-02-14 11:13:39 +010059#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
60 (STM32MP_PARAM_LOAD_SIZE + \
61 STM32MP_HEADER_SIZE))
Yann Gautier4b0c72a2018-07-16 10:54:09 +020062
Yann Gautierb3386f72019-04-19 09:41:01 +020063#ifdef AARCH32_SP_OPTEE
64#define STM32MP_BL32_SIZE U(0)
65
66#define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE
67
68#define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \
69 STM32MP_OPTEE_BASE)
70#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +020071#if STACK_PROTECTOR_ENABLED
Yann Gautiera2e2a302019-02-14 11:13:39 +010072#define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020073#else
Yann Gautiera2e2a302019-02-14 11:13:39 +010074#define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020075#endif
Yann Gautierb3386f72019-04-19 09:41:01 +020076#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020077
Yann Gautiera2e2a302019-02-14 11:13:39 +010078#define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \
79 STM32MP_SYSRAM_SIZE - \
80 STM32MP_BL32_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020081
Yann Gautierb3386f72019-04-19 09:41:01 +020082#ifdef AARCH32_SP_OPTEE
83#if STACK_PROTECTOR_ENABLED
84#define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */
85#else
86#define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */
87#endif
88#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +020089#if STACK_PROTECTOR_ENABLED
Yann Gautiera2e2a302019-02-14 11:13:39 +010090#define STM32MP_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020091#else
Yann Gautiera2e2a302019-02-14 11:13:39 +010092#define STM32MP_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020093#endif
Yann Gautierb3386f72019-04-19 09:41:01 +020094#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020095
Yann Gautiera2e2a302019-02-14 11:13:39 +010096#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
97 STM32MP_BL2_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020098
99/* BL2 and BL32/sp_min require 5 tables */
100#define MAX_XLAT_TABLES 5
101
102/*
103 * MAX_MMAP_REGIONS is usually:
104 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
105 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200106#if defined(IMAGE_BL2)
107 #define MAX_MMAP_REGIONS 11
108#endif
109#if defined(IMAGE_BL32)
110 #define MAX_MMAP_REGIONS 6
111#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200112
113/* DTB initialization value */
Yann Gautier33b96fc2019-04-19 10:55:03 +0200114#define STM32MP_DTB_SIZE U(0x00005000) /* 20Ko for DTB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200115
Yann Gautiera2e2a302019-02-14 11:13:39 +0100116#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
117 STM32MP_DTB_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200118
Yann Gautiera2e2a302019-02-14 11:13:39 +0100119#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200120
121/*******************************************************************************
122 * STM32MP1 device/io map related constants (used for MMU)
123 ******************************************************************************/
124#define STM32MP1_DEVICE1_BASE U(0x40000000)
125#define STM32MP1_DEVICE1_SIZE U(0x40000000)
126
127#define STM32MP1_DEVICE2_BASE U(0x80000000)
128#define STM32MP1_DEVICE2_SIZE U(0x40000000)
129
130/*******************************************************************************
131 * STM32MP1 RCC
132 ******************************************************************************/
133#define RCC_BASE U(0x50000000)
134
135/*******************************************************************************
136 * STM32MP1 PWR
137 ******************************************************************************/
138#define PWR_BASE U(0x50001000)
139
140/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100141 * STM32MP1 GPIO
142 ******************************************************************************/
143#define GPIOA_BASE U(0x50002000)
144#define GPIOB_BASE U(0x50003000)
145#define GPIOC_BASE U(0x50004000)
146#define GPIOD_BASE U(0x50005000)
147#define GPIOE_BASE U(0x50006000)
148#define GPIOF_BASE U(0x50007000)
149#define GPIOG_BASE U(0x50008000)
150#define GPIOH_BASE U(0x50009000)
151#define GPIOI_BASE U(0x5000A000)
152#define GPIOJ_BASE U(0x5000B000)
153#define GPIOK_BASE U(0x5000C000)
154#define GPIOZ_BASE U(0x54004000)
155#define GPIO_BANK_OFFSET U(0x1000)
156
157/* Bank IDs used in GPIO driver API */
158#define GPIO_BANK_A U(0)
159#define GPIO_BANK_B U(1)
160#define GPIO_BANK_C U(2)
161#define GPIO_BANK_D U(3)
162#define GPIO_BANK_E U(4)
163#define GPIO_BANK_F U(5)
164#define GPIO_BANK_G U(6)
165#define GPIO_BANK_H U(7)
166#define GPIO_BANK_I U(8)
167#define GPIO_BANK_J U(9)
168#define GPIO_BANK_K U(10)
169#define GPIO_BANK_Z U(25)
170
171#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
172
173/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200174 * STM32MP1 UART
175 ******************************************************************************/
176#define USART1_BASE U(0x5C000000)
177#define USART2_BASE U(0x4000E000)
178#define USART3_BASE U(0x4000F000)
179#define UART4_BASE U(0x40010000)
180#define UART5_BASE U(0x40011000)
181#define USART6_BASE U(0x44003000)
182#define UART7_BASE U(0x40018000)
183#define UART8_BASE U(0x40019000)
Yann Gautiera2e2a302019-02-14 11:13:39 +0100184#define STM32MP_UART_BAUDRATE U(115200)
Yann Gautier038bff22019-01-17 19:17:47 +0100185
186/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100187#define STM32MP_DEBUG_USART_BASE UART4_BASE
Yann Gautier038bff22019-01-17 19:17:47 +0100188/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100189#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100190#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
191#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
192#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
193#define DEBUG_UART_TX_GPIO_PORT 11
194#define DEBUG_UART_TX_GPIO_ALTERNATE 6
195#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
196#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
197#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
198#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200199
200/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200201 * STM32MP1 TZC (TZ400)
202 ******************************************************************************/
203#define STM32MP1_TZC_BASE U(0x5C006000)
204
205#define STM32MP1_TZC_A7_ID U(0)
Yann Gautiered342322019-02-15 17:33:27 +0100206#define STM32MP1_TZC_M4_ID U(1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200207#define STM32MP1_TZC_LCD_ID U(3)
208#define STM32MP1_TZC_GPU_ID U(4)
209#define STM32MP1_TZC_MDMA_ID U(5)
210#define STM32MP1_TZC_DMA_ID U(6)
211#define STM32MP1_TZC_USB_HOST_ID U(7)
212#define STM32MP1_TZC_USB_OTG_ID U(8)
213#define STM32MP1_TZC_SDMMC_ID U(9)
214#define STM32MP1_TZC_ETH_ID U(10)
215#define STM32MP1_TZC_DAP_ID U(15)
216
Yann Gautierf9d40d52019-01-17 14:41:46 +0100217#define STM32MP1_FILTER_BIT_ALL U(3)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200218
219/*******************************************************************************
220 * STM32MP1 SDMMC
221 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100222#define STM32MP_SDMMC1_BASE U(0x58005000)
223#define STM32MP_SDMMC2_BASE U(0x58007000)
224#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200225
Yann Gautier4baf5822019-05-09 13:25:52 +0200226#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
227#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
228#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
229#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
230#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200231
232/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100233 * STM32MP1 BSEC / OTP
234 ******************************************************************************/
235#define STM32MP1_OTP_MAX_ID 0x5FU
236#define STM32MP1_UPPER_OTP_START 0x20U
237
238#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
239
240/* OTP offsets */
241#define DATA0_OTP U(0)
Yann Gautier3edc7c32019-05-20 19:17:08 +0200242#define HW2_OTP U(18)
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100243
244/* OTP mask */
245/* DATA0 */
246#define DATA0_OTP_SECURED BIT(6)
247
Yann Gautier3edc7c32019-05-20 19:17:08 +0200248/* HW2 OTP */
249#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
250
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100251/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200252 * STM32MP1 TAMP
253 ******************************************************************************/
254#define TAMP_BASE U(0x5C00A000)
255#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
256
257#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
258static inline uint32_t tamp_bkpr(uint32_t idx)
259{
260 return TAMP_BKP_REGISTER_BASE + (idx << 2);
261}
262#endif
263
264/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200265 * STM32MP1 DDRCTRL
266 ******************************************************************************/
267#define DDRCTRL_BASE U(0x5A003000)
268
269/*******************************************************************************
270 * STM32MP1 DDRPHYC
271 ******************************************************************************/
272#define DDRPHYC_BASE U(0x5A004000)
273
274/*******************************************************************************
275 * STM32MP1 I2C4
276 ******************************************************************************/
277#define I2C4_BASE U(0x5C002000)
278
Yann Gautier4d429472019-02-14 11:15:20 +0100279/*******************************************************************************
280 * Device Tree defines
281 ******************************************************************************/
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100282#define DT_PWR_COMPAT "st,stm32mp1-pwr"
Yann Gautier4d429472019-02-14 11:15:20 +0100283#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
Yann Gautier3edc7c32019-05-20 19:17:08 +0200284#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
Yann Gautier4d429472019-02-14 11:15:20 +0100285
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200286#endif /* STM32MP1_DEF_H */