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git01.mediatek.com / filogic / atf / 540ca9e7f98fb7db24f43211b1edb23cf691d33f / . / plat / arm / css / sgi / sgi_bl31_setup.c
blob: ba050d5f1ced9eb909d9203cf8492b4d903ecbcf [file] [log] [blame]
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]1/*
Chandni Cherukuri346a7cc2019-02-27 13:59:11 +0530[diff] [blame]2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]7#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]9#include <libfdt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10
11#include <common/bl_common.h>
12#include <common/debug.h>
Antonio Nino Diaz1b0c6f12019-01-23 21:08:43 +0000[diff] [blame]13#include <drivers/arm/css/css_mhu_doorbell.h>
Antonio Nino Diazc30db5b2019-01-23 20:37:32 +0000[diff] [blame]14#include <drivers/arm/css/scmi.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +0000[diff] [blame]15#include <plat/arm/common/plat_arm.h>
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000[diff] [blame]16#include <plat/common/platform.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]17
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530[diff] [blame]18#include <sgi_ras.h>
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]19#include <sgi_variant.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]20
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]21sgi_platform_info_t sgi_plat_info;
22
Chandni Cherukuri61f3a7c2018-10-11 14:08:08 +0530[diff] [blame]23static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
24 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
25 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
26 .db_preserve_mask = 0xfffffffe,
27 .db_modify_mask = 0x1,
28 .ring_doorbell = &mhu_ring_doorbell,
29};
30
Chandni Cherukuri346a7cc2019-02-27 13:59:11 +0530[diff] [blame]31static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info = {
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]32 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
33 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
34 .db_preserve_mask = 0xfffffffe,
35 .db_modify_mask = 0x1,
36 .ring_doorbell = &mhuv2_ring_doorbell,
37};
38
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000[diff] [blame]39scmi_channel_plat_info_t *plat_css_get_scmi_info(void)
Chandni Cherukuri61f3a7c2018-10-11 14:08:08 +0530[diff] [blame]40{
Chandni Cherukuri346a7cc2019-02-27 13:59:11 +0530[diff] [blame]41 if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM)
42 return &rd_n1e1_edge_scmi_plat_info;
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]43 else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
44 return &sgi575_scmi_plat_info;
45 else
46 panic();
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000[diff] [blame]47}
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]48
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]49void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
50 u_register_t arg2, u_register_t arg3)
51{
Chandni Cherukuri3aa09f72018-11-28 11:31:51 +0530[diff] [blame]52 sgi_plat_info.platform_id = plat_arm_sgi_get_platform_id();
53 sgi_plat_info.config_id = plat_arm_sgi_get_config_id();
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]54
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]55 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
56}
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530[diff] [blame]57
58void bl31_platform_setup(void)
59{
60 arm_bl31_platform_setup();
61
62#if RAS_EXTENSION
63 sgi_ras_intr_handler_setup();
64#endif
65}
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530[diff] [blame]66
67const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
68{
Chandni Cherukuri346a7cc2019-02-27 13:59:11 +0530[diff] [blame]69 /* For RD-E1-Edge platform only CPU ON/OFF is supported */
70 if ((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
71 (sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) {
Chandni Cherukuri2dfe1d02018-11-22 10:15:25 +0530[diff] [blame]72 ops->cpu_standby = NULL;
73 ops->system_off = NULL;
74 ops->system_reset = NULL;
75 ops->get_sys_suspend_power_state = NULL;
76 ops->pwr_domain_suspend = NULL;
77 ops->pwr_domain_suspend_finish = NULL;
78 }
79
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530[diff] [blame]80 return css_scmi_override_pm_ops(ops);
81}