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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleyab2d31e2013-12-02 19:25:12 +00002 * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35
36
37MEMORY {
Achin Gupta4f6ad662013-10-25 09:08:21 +010038 RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
39}
40
41
42SECTIONS
43{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000044 . = BL31_BASE;
45 ASSERT(. == ALIGN(4096),
46 "BL31_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048 ro . : {
49 __RO_START__ = .;
50 *bl31_entrypoint.o(.text)
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 *(.text)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000052 *(.rodata*)
53 __RO_END_UNALIGNED__ = .;
54 /*
55 * Memory page(s) mapped to this section will be marked as read-only,
56 * executable. No RW data from the next section must creep in.
57 * Ensure the rest of the current memory page is unused.
58 */
59 . = NEXT(4096);
60 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010061 } >RAM
62
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000063 .data . : {
64 __DATA_START__ = .;
65 *(.data)
66 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010067 } >RAM
68
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000069 stacks (NOLOAD) : {
70 __STACKS_START__ = .;
71 *(tzfw_normal_stacks)
72 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010073 } >RAM
74
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000075 /*
76 * The .bss section gets initialised to 0 at runtime.
77 * Its base address must be 16-byte aligned.
78 */
79 .bss : ALIGN(16) {
80 __BSS_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010081 *(.bss)
82 *(COMMON)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000083 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010084 } >RAM
85
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000086 /*
87 * The base address of the coherent memory section must be page-aligned (4K)
88 * to guarantee that the coherent data are stored on their own pages and
89 * are not mixed with normal data. This is required to set up the correct
90 * memory attributes for the coherent data page tables.
91 */
92 coherent_ram (NOLOAD) : ALIGN(4096) {
93 __COHERENT_RAM_START__ = .;
94 *(tzfw_coherent_mem)
95 __COHERENT_RAM_END_UNALIGNED__ = .;
96 /*
97 * Memory page(s) mapped to this section will be marked
98 * as device memory. No other unexpected data must creep in.
99 * Ensure the rest of the current memory page is unused.
100 */
101 . = NEXT(4096);
102 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000105 __BL31_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000107 __BSS_SIZE__ = SIZEOF(.bss);
108 __COHERENT_RAM_UNALIGNED_SIZE__ =
109 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000111 ASSERT(. <= BL2_BASE, "BL31 image overlaps BL2 image.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112}