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git01.mediatek.com / filogic / atf / 54078850239861df3d131d8e152c6712b2bdf22f / . / bl31 / aarch64 / bl31_entrypoint.S
blob: 79faf6375cecd8d6d8a34aa98aa5eba8a9a64fe3 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Dan Handleyab2d31e2013-12-02 19:25:12 +0000[diff] [blame]2 * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]31#include <bl_common.h>
32#include <platform.h>
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]33#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]34
35
36 .globl bl31_entrypoint
37
38
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000[diff] [blame]39 .section .text, "ax"; .align 3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]40
41 /* -----------------------------------------------------
42 * bl31_entrypoint() is the cold boot entrypoint,
43 * executed only by the primary cpu.
44 * -----------------------------------------------------
45 */
46
47bl31_entrypoint:; .type bl31_entrypoint, %function
48 /* ---------------------------------------------
49 * BL2 has populated x0,x3,x4 with the opcode
50 * indicating BL31 should be run, memory layout
51 * of the trusted SRAM available to BL31 and
52 * information about running the non-trusted
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]53 * software already loaded by BL2.
54 * ---------------------------------------------
55 */
56
57 /* ---------------------------------------------
58 * Set the exception vector to something sane.
59 * ---------------------------------------------
60 */
61 adr x1, runtime_exceptions
62 msr vbar_el3, x1
63
64 /* ---------------------------------------------
65 * Enable the instruction cache.
66 * ---------------------------------------------
67 */
68 mrs x1, sctlr_el3
69 orr x1, x1, #SCTLR_I_BIT
70 msr sctlr_el3, x1
71
72 isb
73
74 /* ---------------------------------------------
75 * Check the opcodes out of paranoia.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]76 * ---------------------------------------------
77 */
78 mov x19, #RUN_IMAGE
79 cmp x0, x19
80 b.ne _panic
81 mov x20, x3
82 mov x21, x4
83
84 /* ---------------------------------------------
85 * This is BL31 which is expected to be executed
86 * only by the primary cpu (at least for now).
87 * So, make sure no secondary has lost its way.
88 * ---------------------------------------------
89 */
90 bl read_mpidr
91 mov x19, x0
92 bl platform_is_primary_cpu
93 cbz x0, _panic
94
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000[diff] [blame]95 /* ---------------------------------------------
96 * Zero out NOBITS sections. There are 2 of them:
97 * - the .bss section;
98 * - the coherent memory section.
99 * ---------------------------------------------
100 */
101 ldr x0, =__BSS_START__
102 ldr x1, =__BSS_SIZE__
103 bl zeromem16
104
105 ldr x0, =__COHERENT_RAM_START__
106 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
107 bl zeromem16
108
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]109 /* --------------------------------------------
110 * Give ourselves a small coherent stack to
111 * ease the pain of initializing the MMU
112 * --------------------------------------------
113 */
114 mov x0, x19
115 bl platform_set_coherent_stack
116
117 /* ---------------------------------------------
118 * Perform platform specific early arch. setup
119 * ---------------------------------------------
120 */
121 mov x0, x20
122 mov x1, x21
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]123 bl bl31_early_platform_setup
124 bl bl31_plat_arch_setup
125
126 /* ---------------------------------------------
127 * Give ourselves a stack allocated in Normal
128 * -IS-WBWA memory
129 * ---------------------------------------------
130 */
131 mov x0, x19
132 bl platform_set_stack
133
134 /* ---------------------------------------------
135 * Use SP_EL0 to initialize BL31. It allows us
136 * to jump to the next image without having to
137 * come back here to ensure all of the stack's
138 * been popped out. run_image() is not nice
139 * enough to reset the stack pointer before
140 * handing control to the next stage.
141 * ---------------------------------------------
142 */
143 mov x0, sp
144 msr sp_el0, x0
145 msr spsel, #0
146 isb
147
148 /* ---------------------------------------------
149 * Jump to main function.
150 * ---------------------------------------------
151 */
152 bl bl31_main
153
154_panic:
155 b _panic